Understanding MCU Block Diagram

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Understanding MCU Block Diagram

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ARM Cortex M Microcontroller DMA Programming Demystified

Direct Memory Access Demystified with STM32 Peripherals (ADC, SRAM,UART,M2M,M2P,P2M) and Embedded C code Exercises

09:42:49 of on-demand video • Updated December 2023

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Fundamentals of Direct Memory Access in a Microcontroller
The Microcontroller Architecture and Bus interfaces
Bus matrix of the ARM cortex M based MCU
Concurrent data access from ARM and DMA
DMA control configurations like burst size, FIFO, Alignment
DMA Controller internals and Bus interfaces
DMA Controller channels,Streams,priority
Memory to Memory data transfer using DMA and Exercises
Peripheral to Memory and Memory to Peripheral DMA and Programming exercises
Peripheral DMA configurations
DMA controller interrupts and interrupts handling
All right. Welcome back to the lecture and in the previous lecture you just saw some basic concept about the direct memory access. And we also explored about the Slave and Master communication. Isn't it? And now let's look at the block diagram of one particular microcontroller, to see how exactly the architecture looks like and what are all the masters as well as slaves present in the system. And after this lecture you can open your documentation like datasheet, or reference manual, and you can analyze this. All right. Great. So, now here I have opened the datasheet of the STM32F4 series of microcontroller. So, the exact part number is this one. This I found in the datasheet of this microcontroller you cannot locate this in the reference manual, and here I have also opened the reference manual. OK. So, this is my reference manual and so let me open this section here memory and bus architecture, and here let's open system architecture. So, the reference manual says that there are 7 masters. So, there are 7 slaves. Now, Cortex M4 with FPU core I -bus, D-bus and S-bus. So, totally there are 3 masters. This is a 4th one, this is a 5th one, and this is 6th, and this is the 7th master. And there are 7 slaves. So, now let's locate them in the diagram OK. So, here is a ARM Cortex M processor and these are the 3 bus interfaces provided by the ARM to connect to the external world. Isn't it? So, this I-bus actually originates from the AHB bus master which is sitting inside the ARM processor. The D-bus is also controlled by another AHB bus master. And system bus is also controlled by another AHB bus masters sitting inside the processor. So, totally there are 3 bus masters OK. Or you can also called it as AHB ports, master ports, present in the processor. That's why, there are 3 masters here. All right.So, now let's move forward and here it is the next master is DMA1 memory bus. So, here is the DMA1 and it actually gives out 2 buses. And one is actually a memory bus and another one is a peripheral bus. OK. So, here what you are saying here it is a memory bus. And what you're seeing here which is actually not going into the AHB it is taking a turn here. Isn't it? So, this is called as peripheral bus. And about memory bus and peripheral bus so it discuss later. And these 2 buses are controlled by the AHB master ports sitting inside the DMA1 controller. So, that we will see later. And here is a DMA2, and DMA2 also gives out 2 busses. So, this is a memory bus and this is a peripheral bus. OK. And both are controlled by the AHB masters sitting inside the DMA2 controller, and the next master is the USB OTG High speed. So, this is a also one of the master which is present in this microcontroller. So, totally they say that it has 7 masters and now let's take a look into the slaves. So, let's start from the bottom. So, now as you know a microcontroller will be having lots of bus interfaces, and it has lots of peripherals hanging onto different bus interfaces. Isn't it? So, now at your left hand side what you are seeing here is lots of peripherals, which are hanging onto the APB 2 bus. And in the right hand side also you are seeing lots of peripherals here which are hanging on to the APB 1 bus. Isn't it? So, this is a APB 1 bus and this is a APB 2 bus. And finally, both the buses are touching this bridge. Right? And then they are connected back to the main bus, that is AHB1. So, what we can say now is the peripherals which are hanging onto the APB 2 bus. And APB 1 bus can be treated as one slave, that is this one. AHB1 peripherals including AHB to APB bridges and APB peripherals. The whole slaves which are comes under AHB1. Right? So, all these peripherals are finally they connected back to the AHB1 through this bridge. Right? So, all those peripherals which are controlled by the AHB1 is considered as 1 slave, that is AHB1 peripherals. Now, for example, let's say timer 10. So, timer 10 is a slave which comes under this category. OK. So, because the timer 10 finally it communicates to the processor over the AHB1 bus. Right? So, even though it is hanging onto APB bus.The APB bus finally goes and touches this bridge. And from this bridge only the signal then transfer to the AHB bus and then it will be you know connected to the processor. Isn't it? via the bus matrix. Now, apart from that AHB2 peripherals.Here is a AHB2 bus. Right? So, which is also touching to the bus matrix. So, we'll be discussing about the bus matrix later. So, don't worry about that and this AHB2 bus is carrying 2 peripherals OK. One is a camera interface and another one is a USB OTG full speed PHY. So. So, these 2 are considered as another peripheral another slave. So, that comes under this category AHB2 peripherals. And the next one is FMC and QUADSPI. So, which are connected to the bus matrix here, and these are called as next slaves. OK. So, which are connected over this bus. So, that is also another AHB bus. OK. To the bus matrix. And after that, Auxiliary internel SRAM2. OK. So, that is this one which is directly connected to the bus matrix and also the SRAM1 which is also connected to the bus matrix. So, these 2 are also considered as slaves. So, the next one is the Internal Flash memory ICode bus and Internal Flash memory DCode bus. So, here is a internal flash and that is actually connected to the flash controller here, that is the flash interface. And these are considered as 2 slaves. So, this is a ICode bus of the flash engine remember OK. And this is the DCode bus of the flash engine. And those 2 are also considered as slaves. Let's say, and the processor you know if it wants to fetch instruction from the flash, it actually does that over the I-bus. Which comes over this bus matrix and then talks to the ICode of the flash here in order to fetch the instruction. And if the processor wants to read some Read-Only data from the flash, than it reads that over this decode and it finally comes over this bus matrix and touches this DCode interface and then it reads the data. So, these 2 interfaces are considered as slaves another 2 slaves. So, totally there are 7 slaves. So, we have identified these slaves and masters on the microcontroller. Mainly the processor, the USB, and the DMA is are the masters in this microcontroller. Some people may be wondering what exactly is this AHB bus matrix. So, that is actually very very important topic should be covered in order to understand the DMA properly. OK. So, in the next lecture I will try to cover the AHB bus matrix and I will see you in the next lecture.