MCU Bus Interfaces Explanation Part 3: Q/A session

Hey, welcome back to the course. So, in the previous lecture what we did was we just explored about the MCU block diagram in the case of STM32F4 series of microcontroller as well as we also explored the block diagram. A High level a Block Diagram of TIs Tiva series of micro-controller. And as I said, if you have any other micro-controller from a different vendors then you just go and check in your data sheet or reference manual to understand the block diagram. Because, I cannot cover all the microcontroller which is there in the market. Right? I can only point to, to the generic concept so which you can average to understand your microcontroller. And as I compare these two block diagrams they are almost same, but there are some minor differences but the architecture is almost the same. Great!! So, now in this lecture what will do is, we will just discuss some questions and answers. So, these are some of the thought provoking questions on whatever we learned so for and the reference for this question is a STM32F446RE micro controller. Great!! So, now let's go to the question one by one. The first question. Is it true that, System Bus is not connected to FLASH memory? So, take five seconds to think this answer. The answer is true. Isn't it? So, if you check in the section embedded Flash memory interface in the reference manual you see this diagram. So, here you can see that flash is actually connected to ICode and DCode. So, you can see that this line S- Bus is not going to flash memory. So, that proves that in this microcontroller the flash is actually connected to the Cortex Core over ICode and DCode and the system bus is not connected to flash memory. That's true. Now, the second question. Processor can fetch instructions from SRAM over ICode bus interface. True or false? So, what is your answer for this. So, for a time being I will say this answer as false, but that is actually not true. There are some advanced techniques by which you can make your processor to fetch instructions from SRAM over the ICode bus .That's possible that will see later. So, let's not worry about that but for the time being I will say False. System bus can operate at the speed up to 180 MHz? So, the answer for this is here 180MHz. That's true. The Cortex processor can run up to you know speed of 180 MHz. Great!! So, that means the system bus can also run up to the speed of 180MHz. That's true. Great!! So, now SRAMs are connected to system bus True or false? That's correct. Right? The SRAM they are actually connected to the system bus over this bus matrix. Don't worry, I will explain the Bus Matrix later in the next lecture. So, now next question .APB1 bus can operate at the speed up to 180 MHz? So, what's your answer for this. Can APB1 bus operate at the speed of 180MHz? That's not true I think. Because, APB1 bus as they mentioned here it can only run up to 45MHz. So, that means. So, this is false. Let's say, I have a peripheral whose data sheet says that, it's operating frequency or speed must be above 95MHz, Can I connect that peripheral via APB2 bus? So, here there is a device or a peripheral, which must run at 95 MHz to behave properly. Then, can you connect that peripheral to processor via APB2 Bus. So, what is the maximum frequency of APB2 Bus? Maximum operating frequency of APB2, it is 90 MHz. Right? So, then it's not possible you cannot connect it. Now, next question, Processor can fetch instructions as well as data simultaneously from SRAM. True or false? So, just think about this answer. Can processor fetch instructions and data simultaneously? No right. It's not possible. This is false. Right? Because, there is only one bus which connects to SRAM. So, it has to first read the instructions then it has to read the data, right? simultaneously and it cannot read it. Right? So, that's not possible. So, Processor can fetch instructions as well as data simultaneously from FLASH. True or false? So, what's your answer. This is true right. It can fetch simultaneously, because it has separate bus called ICode and DCode Right? All right. So, now next question. What is the Max.HCLK OK so now this is a repeater. So, what is the maximum HCLK value of your MCU? So, in this case I'm considering this MCU. So, what is the maximum HCLK value? All right. So, remember that HCLK is a notation or abbreviation used to describe the clock frequency or operating clock frequency of the AHB Bus. So, if you go back to our diagram here. So, this is the AHB bus that is AHB1 bus, which has the capacity to run maximum speed up to 180MHz and we have also AHB2 bus, which also has the capacity to run at maximum at 180 MHz. OK. You can even lower the frequency. So, that's possible. And the current operating frequency of the AHB bus is denoted by the term HCLK. So, now the answer for this question is 180MHz. Now, the next question. What is the maximum P1CLK value of your MCU? The P1CLK is actually the abbreviation used to denote the clock frequency the operating clock frequency of the APB1 bus. It's operating frequency actually denoted by P1CLK. So, P1CLK maximum P1CLK is 45MHz. Right? And the P2CLK means, the operating clock frequency of the APB2 Bus. So, that is the maximum value you can use for P2CLK is 90 MHz. Right? Great!! So, now next question. GPIOs and processor communicate over AHB1 bus True or false? So, where is your GPIO, this is your GPIO. And where is your processor, this is your processor. So, they both communicate over AHB1 bus. That's true. Because, it is connected to AHB1 bus and further from here to here the connection is actually through system bus. So finally, this AHB1 bus goes and connects to S-Bus. And please remember that finally everybody should go and connect to system bus through the Bus Matrix .So, Bus Matrix is a you know your traffic controller kind of guy who actually decides, a which bus to connect for a given point in time. That means Bus Matrix will actually serialize the access. So, the answer for this question is GPIO connects to ARM processor over AHB1 bus via the system bus to the processor. So, USB OTG and processor communicate over AHB2 bus. True or false? . That's true, because here is a USB OTG peripheral that is actually connected to AHB2 Bus. And finally it is connected to a Bus Matrix, then it will talk to the Cortex processor over System bus. Great!! That's true. Right? Now, next question. USB OTG and GPIOs can communicate to processor concurrently or simultaneously. Is it true or false? A very interesting question. So, my answer would be false. Because, it has to be serialized. Right? So, this guy and this guy finally even though they have connected to different AHB buses, so the moment they want to talk to System bus ,the Bus Matrix will serialized the access .It's not possible to communicate simultaneously. It's not possible. Processor can talk to flash memory and SRAM simultaneously? So, what's your answer for this. The processor here is a processor can talk to the flash and the SRAM simultaneously. That's true right. Because, there are dedicated busses. Right? The processor can talk to flash over ICode and DCode and at the same time it can talk to the SRAM over System bus. So, what's the problem. It can do that. Right? So, now that leads to our next discussion that is AHB Bus Matrix. So, that actually serializes you know communication between the controller and the various peripherals on different buses. Great!! So, now I hope you understood and if you have any questions then please raise your questions and I will see you in the next lecture.