Microcontroller Architecture with Embedded Systems

Hello and welcome! In the last lesson we discussed about the micro-controller, its general architecture and the difference between the general purpose microprocessor and the microcontroller. In this lesson we shall learn about the processor architecture. We shall understand the different architectures. One based on the design of instruction set and the other based on the memory organization. In the last lesson I stated the microcontrollers use reduced instruction set architecture and microprocessors are based on complex instruction set architecture. So what is the instruction set architecture? Based on the characteristics of instruction supported the architecture of a microprocessor is classified into reduced instruction set computer and complex instruction set computer. These are known as RISC and CISC in short respectively. The RISC architecture implements the instruction set that contains large number of complex instructions. A CISC instruction can be split into several simple instructions called micro instructions executed by the microprocessor. The CISC architecture optimizes the size of executable image by emitting less number of instructions for a program. The CISC machine has a few CPU registers and the instructions process the operands those are stored in computer's memory. The instruction of a CISC machine are encoded using variable word width. That means there is no uniformity in the number of bits used to encode different instructions. Also the clock cycles per instructions are different for different instructions. Due to these characteristics the CISC processor either do not implement CPU pipelining or have limited pipeline stages. The CPU pipeline is discussed in detail in the later sections with reference to the ATmega328 micro-controller. The compiler used for generation of executable code is relatively simple for CISC processors. The Intel's x86 series of processors and Motorola 68K family are based on CISC architecture. The risk architecture provides limited yet simple set of instructions. These instructions carry out a simple step during program execution. Since the instructions are simple, these are executed mostly in single clock cycle and most of the instructions are encoded using fixed word width. The underlying hardware design is also simpler compared to that of a RISC processor. Since the instructions have the fixed word width, the RISC processor implement highly effective multistaged CPU pipelining. In a pipelined CPU the different stages of instruction execution is overlapped among subsequent instructions. This increases utilization of different functional components of a CPU and enhances instruction execution throughput. However pipelining increases hardware complexity of a processor. The RISC machine has huge number of general purpose CPU registers and most of the instructions take operands stored in these registers. RISC processors provide dedicated instructions to move data between registers and memory. The executable code generated for a RISC machine is lengthy than that of a CISC machine. And the compiler design for a RISC machine is complex. Atmel's AVR family of microcontrollers, ARM's CortexM series of microcontrollers and several other microcontrollers implement RISC architecture. The table soon summarizes the important differences of RISC and CISC architecture. Another architectural classification is based on the organization of memory. These are Harvard architecture and Von Neumann architecture. The Von Neumann architecture is also known as Princeton architecture. In the Von Neumann architecture, the CPU interacts with single memory. That means the program code and the program data is stored in the same memory during program execution. In contrast the Harvard architecture uses different memory units to store the program code and program data. These memory units are accessed using different buses. The Von Neumann architecture became popular in early days as it simplified the process design. However these CPUs cannot access the program memory and the data memory simultaneously which imposes bottlenecks and affected the system's performance. On the other hand the CPUs based on Harvard architecture can independently access the program and data memory. Thus it could execute the instructions in fewer clock cycles. This is because a much greater amount of instruction parallelism is possible in the Harvard architecture. The modern computers do not have physically separate memory spaces for program code and program data. So technically it can be described as Von Neumann architecture but this architecture is termed as modified Harvard architecture. These processors might share memory between program code and data but implement special instructions that keep data from being mistaken for code. However modified Harvard architecture have two seperate buses to access the program called and program data while the memory is one shared physical piece. With this we come to the end of this section. I hope this section has provided clear and concise introduction to the embedded system and microcontrollers. In the next section we shall set up the development environment and the development board. Till then Happy learning. Thank you.