Understanding Multi AHB Bus Matrix

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Understanding Multi AHB Bus Matrix

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ARM Cortex M Microcontroller DMA Programming Demystified

Direct Memory Access Demystified with STM32 Peripherals (ADC, SRAM,UART,M2M,M2P,P2M) and Embedded C code Exercises

09:42:49 of on-demand video • Updated December 2023

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Fundamentals of Direct Memory Access in a Microcontroller
The Microcontroller Architecture and Bus interfaces
Bus matrix of the ARM cortex M based MCU
Concurrent data access from ARM and DMA
DMA control configurations like burst size, FIFO, Alignment
DMA Controller internals and Bus interfaces
DMA Controller channels,Streams,priority
Memory to Memory data transfer using DMA and Exercises
Peripheral to Memory and Memory to Peripheral DMA and Programming exercises
Peripheral DMA configurations
DMA controller interrupts and interrupts handling
Hey, welcome back. So, in the previous lecture we identified masters and slaves in our block diagram, but we still have some doubts regarding the bus matrix and how exactly this master and slaves communicate.Grate. So, for that we have to look into the bus matrix diagram, which is just given below in this document. Here it is Multi-AHB bus matrix. And if we just browse through this document here you will get one nice diagram and let me just copy this diagram to my presentation. All right. So, now I'm ready with this diagram and here the circuitry what you are seeing here all these connected dots and these vertical and horizontal lines. This is actually called as Multi AHB bus matrix. And all these are called masters so we can name them, this is the M1, this is M2, this is M3, M6, and M7. So, here this is also actually another master but, since it is not touching the bus matrix. So, we are just not naming it. That's it. So, strictly speaking these buses are not masters. These buses are governed by AHB master port here, that is inside this processor here. So, we actually call them as masters. Great. So, now there are 7 slaves, this is S1, S2, and S7. So,7 slaves. Consider this ARM Cortex M4 master1 that is the ICode bus.Now, So, when you trace this vertical line you see 3 connected dots here. Right? So, those are actually fuses given by the bus matrix. The bus matrix like electronic fuses which connects various masters to the various slaves. Now, let's consider only this master. So, now this master can talk to the slave 1.So, because there is a fuse it can talk to slave 3, that is actually the SRAM 1 and it can also talk to the slave 7. That is actually the external memory controller. So, the I-bus here cannot talk to the let's say the SRAM 2 or it cannot talk to the AHB 2 peripherals, and cannot even talk to the AHB1 peripheral. So, why ARM uses I-bus? It actually uses I-bus in order to fetch instructions. Isn't it? So, this also means that it can only fetch instructions from flash, that also through the ICode interface, it can fetch instructions from the SRAM and it can also fetch instructions from the external memory which is connected to the external memory controller. So, that means it cannot execute instructions from peripherals. OK. So, here there are no fuses. Isn't it? And this also indicates that the ARM processor can fetch instructions from SRAM1 over the ICode bus, it's possible. So, you see this connection here. Grate. So, now let's talk about D-bus. So, D-bus for D-bus there are also 3 connections. So, it can talk to the second slave, it can talk to the third slave, and it can talk to the seventh slave. This path clearly indicates that decode bus fetches the read only data or data from the flash memory over this decode bus interface. And it can also fetch data from the SRAM. That's possible. But it cannot fetch data from the SRAM2. There is no connection. All right. So, now let's see the system bus.For system bus here there are 4 connections. Let's say, you have kept some instructions in the SRAM1. And by default you know ARM executes instructions from flash. Isn't it? So, that is also through the ICode interface. But, now let's say you have stored some instructions in the SRAM 1 and now you jump to the SRAM location, that is you program the PC with the address of the SRAM1. So then, what processor does? That's OK. The processor actually now fetches the instruction over the SRAM1 it can do that, because there is connection. And processor can use S-bus in order to fetch the data also from SRAM1. If you use I-bus and D-bus in order to execute instructions and to fetch data, it can do simultaneously because I-bus is going to the flash and D-bus is also going to the flash. So, it can fetch instruction over this bus and it can fetch data over this bus. Right? So, simultaneously that will actually boost the performance. But, if you use system bus in order to execute instructions, then what happens. OK. So, it has to use system bus in order to fetch instructions from the SRAM. Right? So, then the data access and the instruction access has to be serialized OK. So, because there is only one bus through which you have to fetch instructions as well as the data. OK. That also means that, if you use system bus in order to execute instructions the performance will be slower. But, if you use I- bus and D-bus interface in order to fetch instructions and data. Since, there are 2 parallel buses performance will be more. And now, you can also see that the system bus is also connected to the SRAM2, it can talk to the SRAM2 and system bus can also talk to the AHB2 peripherals and AHB1 peripherals. So, that means this bus map is clearly indicates that all the AHB2 peripherals and AHB1 peripherals, they finally talked to the processor over the system bus only. Because, there are no connections here. Grate.So,now let me erase everything. Now, let's come to the DMA1. And in the DMA1 it has actually 2 ports, master AHB ports here which actually give out two buses here. One is called this DMA peripheral interface or peripheral bus and DMA memory bus. The memory bus is actually again connected to the bus matrix and it has the capacity to access all these slaves. Whereas the peripheral bus is connected all the way to here it is. It is connected all the way to the APB1 bus. OK. So, that we can verify by using the block diagram here. So, here it is. This is the DMA 1 bus is coming all the way to APB1 bus. OK. So, then finally you know it touches the APB1 bus here. OK. So, that's what shown here. This path. Great. So, now and the DMA2 also you know gives out 2 buses. One is peripheral bus, which is going to goes to APB2 bus. And that peripheral bus is also connected to the bus matrix, so that the peripheral bus has the capacity to access all these slaves. OK. So, where as this peripheral bus can only talk to the peripherals of the APB1 bus. Right? But, in this case the peripheral bus has the capacity to talk to the APB2 bus as well as all these other slaves. Right? So, this has got more religious privileges than this. And finally the DMA memory bus of the DMA2 controller can talk to all these peripherals. Great. So, that means in summary what I want to say is, bus matrix is electronics circuitry you can consider like that. Those fuses actually decide the master and slave communication privileges. OK. So, you just saw that the I-bus master can only talk to 3 slaves. So, that's the privilege given in this design. OK. So, this design may be different in another microcontroller. All right. Great. So, that's the bus matrix, who decides the master and slave communication. And all the communication finally go through this bus matrix. So, let's take an example for that. Let's take an example, let me erase everything and let me go to the block diagram. Let's say, the SPI 4 peripheral. Now, the SPI peripheral is actually connected to the APB 2 bus. Right? So, now let's say the SPI has some data to be transferred to the memory. Then, how does it work? Let's find out by using bus matrix. So, SPI is connected to APB 1 bus and let's forget about DMA. So, let's say let's assume there are no DMA controllers or DMA controllers are not active. Now, SPI has to exchange data, how it happens? From peripherals it will come to APB1 bus. From APB1 bus it goes to AHB. Right? Why? Because, it's finally it goes and touches the AHB bus. Right? Here it is. This is AHB. Right? Right? So, it comes over here like that. It comes over here, I said DMA's are not active. It comes here. Now, it has to take this path. Right? Because there is a fuse. It goes over the system bus to the internal register of the ARM, then ARM executes store instruction and that store instruction has to utilize the system bus. Right? And according to the address it goes to the memory. All right. So, this is a path. So. So,hope you are understanding this, and let's say, if you now use DMA for the SPI peripheral. In order to transfer data what happens. So, this is non DMA case. Now, if you use DMA what happens. SPI1 is connected to the APB1 that we know. Now, the data instead of going to AHB1, where it goes? here it is. The data comes all the way to the bridge and from bridge instead of taking AHB path here it takes this DMA path. Right? So, what happens. It takes the DMA path, so this is a DMA path. Comes all the way to the DMA 1 peripheral bus takes a U-turn and comes to the SRAM. So, look this path. This path is actually outside the bus matrix, that is it has got another bus and then it comes to the memory. So, this is the case of this is with the DMA1 with the help of DMA1. So, that's the data transfer and the data has to be moved from the bus matrix to the master from slaves, and some time with the help of DMA you can avoide the bus matrix. So, as you saw here. OK. So, finally if it wants to talk to the memories, it has to go through the bus matrix. Great. So, now in the next lecture analyze this again with one important use case. OK. I will see you in the next lecture.