This System Verilog course teaches the System-On-Chip design verification used in VLSI industry. This will be a good starting point to learn System-Verilog language for IC/SOC verification. It covers the fundamentals of the language and explain the concepts from the basics.
This course contains video lectures of 1 hour duration. It is stared by explaining what is design and verification code in System Verilog and how they are different. It explains the language constructs like datatypes, arrays and operators in next session with examples. Different kind of assignments in SV are explained in detail with their behavior in simulation. The control flow statements and looping statements are demonstrated in the next session. Finally, the thread launching mechanism is explained at the end
By taking this course, the a student will be able to start learning System Verilog for verification and master it slowly. This course will also be helpful for the HDL programmers who know something about SV programming but not clear about its structured writing.
A post graduate in electronics engineering with 8+ years of industrial experience in ASIC design and Verification using System Verilog at major semiconductor companies. A passionate and continuous learner in emerging technologies in VSLI and also interested in other technical domains related to programming. Finds energy in learning new technologies and and sharing knowledge with others.