Design Verification Engineer
Having more than 7 years experience in VLSI design having experience in verilog and system verilog & UVM. I worked on protocols like AHB, APB and AXI which are essential modules in VLSI design. I worked on different project covered more than 50 verilog modules. I have experience on FPGA boards, and xilinx Zynq FPGA boards (which having ARM processor in it). I am planning to do future courses on AMBA protocols and General Microprocessor design with our own Instruction Set Architecture (ISA).