An Engineer by degree and a life-long student. A VLSI enthusiast focusing majorly on Physical Design domain. My work primarily revolves around block and SoC design planning using opensource EDA tools. Associated with three standalone PnR projects on Skywater 130nm and osu 180nm pdks and currently working on efabless' Openlane (RTL2GDS) flow project; aimed at complete automation of all stages from RTL to all the way down to GDSII.
AFFILIATIONS:
Research Intern at VLSI System Design (VSD) Corp. Pvt. Ltd.
