I am a senior verification engineer with around 20 years experience in ASIC functional verification.

I have contributed to the successful completion of projects ranging from start-ups to well established companies.

Professional Experience:

- 20 years experience as a functional verification engineer using 'e'​ language and SystemVerilog

Technical Specialties:

- Master of Engineering in Microelectronics

- Functional verification at block level and system level using constrained random verification

- Verification components development

- Programming Languages: 'e'​, SystemVerilog, Java, Kotlin, Python, C#, Swift

- Verification Methodologies: UVM, eRM

- EDA Tools: Incisive (Cadence), Questa (Siemens), VCS (Synopsys)