Learn VHDL and FPGA Development
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Learn VHDL and FPGA Development

Learn how to create a VHDL design that can be simulated and implemented on a Xilinx or Altera FPGA development board.
Best Seller
4.6 (383 ratings)
Instead of using a simple lifetime average, Udemy calculates a course's star rating by considering a number of different factors such as the number of ratings, the age of ratings, and the likelihood of fraudulent ratings.
3,521 students enrolled
Created by Jordan Christman
Last updated 8/2017
English
English [Auto-generated]
Current price: $10 Original price: $100 Discount: 90% off
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Includes:
  • 4.5 hours on-demand video
  • 5 Articles
  • 31 Supplemental Resources
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
What Will I Learn?
  • Understand the design process for implementing a digital design onto a FPGA
  • Learn how to simulate a design in Altera’s ModelSim and Xilinx Isim
  • Learn how to use Xilinx ISE tool to program FPGA
  • Debug a VHDL design using ModelSim
  • Simulate a VHDL design using ModelSim
  • Familiarize yourself with Altera and Xilinx tools
  • Program a FPGA
View Curriculum
Requirements
  • Purchase a BASYS 3 or BASYS 2 FPGA Development Board
  • Download Xilinx ISE webpack if your using the BASYS 2, but we will cover that in this course!
  • Download Vivado if your using the BASYS 3 board, we will cover this in the course!
  • Basic understanding of Binary Notation
  • Basic understanding of Hexadecimal Notation
  • Basic understanding of Logic Gates
Description

This course supports both the Xilinx and Altera FPGA development boards.

VHDL and FPGA Development for Beginners and Intermediates is a course that is designed to teach students how to create and successfully simulate their VHDL design. We will also be implementing these designs on a Xilinx BASYS 3 or BASYS 2 FPGA development board so that the students can see their designs actually running. This course starts from beginning to end in teaching the user how to turn their digital logic design into VHDL designs that can be simulated in ModelSim or ISim and then implemented on an FPGA development board. This course also covers how to use Altera's tools so students are not limited to Xilinx development boards.

Course Structure:

This course contains over 20 lectures that will teach students the syntax and structure of VHDL. The student will be able to understand the syntax and use of specific VHDL keywords by taking this course. There are lectures included in each lab to give a background on the digital logic circuit the student will be implementing.

This course contains 7 labs that are designed so that the student will learn how to develop VHDL code. For each lab I will give the student a set of VHDL files that they will have to modify or change in order to get the project to simulate correctly in ModelSim and so they can implement the design on their FPGA board. These labs are design to help the students learn VHDL by actually coding it themselves.

Please message me before you sign up for this course!

Who is the target audience?
  • Engineering Students
  • Engineering Managers
  • Digital Logic Enthusists
  • Individuals pursuing Electrical Engineering
  • Anyone who wants to take it for fun!
Compare to Other FPGA Courses
Curriculum For This Course
85 Lectures
13:09:03
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Contact Information
2 Lectures 00:09

This contains the information required to contact me, please download and use this if you have any questions.

Contact Information
1 page

If you are interested in learning more about FPGA development, these links contain resources that cover more advanced FPGA development topics.

Preview 00:09
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Introduction
2 Lectures 09:35

This lecture introduces this course, I will introduce myself as well as explain what will be covered in this course. The course layout is explained in this course.

Preview 03:42

Introduction to VHDL and the different ways you can use VHDL. This will give you a better understanding of what VHDL is doing and how it differentiates from a software programming language.

Introduction to VHDL
05:53
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VHDL Data Types
8 Lectures 36:28

This lecture introduces the various data types used in the VHDL language. All of these data types are then explained more thoroughly in the later lectures.

Data Types Introduction
02:56

This lecture talks about what variables, signals, and constants are and how they are used in the VHDL language.

Signals / Variables / Constants
04:27

This lecture discusses signed and unsigned data types in the VHDL language.

Unsigned / Signed Data Types
05:15

This lecture discusses the VHDL data types standard logic vector and standard logic.

Standard Logic Vector / Standard Logic
04:27

This lecture talks about the Integer and Boolean data types in VHDL.

Integer / Boolean Data Types
03:46

This lecture walks through an example VHDL file that shows various data types in VHDL being initialized.

Initializing Values in VHDL
07:32

This lecture walks through a VHDL design while talking about the various data types being used in the VHDL language.

Data Type Examples in VHDL Designs Part 1
05:46

This lecture takes students through an example VHDL design and discusses the various data types being used throughout the design.

Data Type Examples in VHDL Designs Part 2
02:19
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VHDL Syntax
7 Lectures 31:45

This lecture introduces the VHDL Syntax section and explains everything that will be covered in this section.

VHDL Syntax Introduction
01:08

If statements and case statements are commonly used in various programming languages. These statements are also used in VHDL and I will explain how in this lecture.

If Statement / Case Statement
07:34

This lecture walks through and discusses how for loops and while loops are used in VHDL.

For Loop / While Loop
06:33

This lecture explains the differences between a for loop in VHDL verses a for loop in a software programming language such as c++.

VHDL For Loop Example
03:50

This lecture discusses two different statements in VHDL, the when-else statement as well as the with-select-when statement.

When Else Statement With Select When Statement
04:16

In VHDL things happen concurrently by nature, however with the use of processes and variables we can make things happen sequentially. In this lecture I will discuss the difference between them.

VHDL Processes and Concurrent Statement
05:04

This lecture walks through a VHDL design and discusses the layout and structure of the VHDL syntax.

VHDL Syntax Design Example
03:20

This is a quiz that goes over the material covered in section 2 VHDL Language Basics

1 VHDL Basics
5 questions
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VHDL Coding Structure
6 Lectures 23:16

This lecture shows students a way they can organize their VHDL designs. As you create more designs it becomes important to organize them in a way it's easy to find and re-use your designs.

Organizing Your VHDL Designs
03:00

This lecture talks about the various aspects of a VHDL design and the structure of these designs.

VHDL Design Structure
05:15

This lecture discusses the different architecture design styles used in VHDL designs.

VHDL Design Architecture Styles
09:01

This lecture walks through a full adder VHDL design. this full adder design is implemented using a data flow architecture style.

Data Flow Architecture Example - Full Adder
03:25

This lecture walks through a full adder VHDL design. this full adder design is implemented using a behavioral architecture style.

Behavioral Architecture Example - Full Adder
02:06

Concept of VHDL Modeling
00:29

This quiz is used to test your understanding of VHDL coding structures.

VHDL Coding Structure
10 questions
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Test Bench
3 Lectures 09:55

This lecture explains what a test bench is and how they are used in the VHDL language.

Test Benches Introduction
04:11

This lecture walks through the design of a test bench and explains the structure of a VHDL test bench.

Test Bench Structure Walkthrough
02:35

This lecture walks through a completed test bench as an example of how a test bench is constructed.

Walkthrough of a Completed Test Bench
03:09
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Implementing State Machines in VHDL
2 Lectures 04:56

This lecture introduces state machine in VHDL and explains how they are used.

State Machine Introduction
03:59

This article explains how to design a state machine. There are various ways to design a state machine and this article covers one of them.

Designing a State Machine
00:57
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FPGA Development Boards
8 Lectures 12:41

This article lists various FPGA development boards that students could use to complete this course. FPGA development boards not listed in this article can still be used, just message me and see if your board will work!

Supported FPGA Development Boards
02:03

This lecture is an overview of the BASYS 3 development board.

Preview 04:42

This is the user guide provided by digilent that explains all the different components and aspects of the BASYS 3 development board.

BASYS 3 Board User Guide
19 pages

The schematic of the BASYS 3 development board.

BASYS 3 Board Schematic
7 pages

An overview of the BASYS 2 FPGA development board.

BASYS 2 Board
01:48

This lecture contains the BASYS 2 user manual provided by digilent.

BASYS 2 Board User Guide
12 pages

This is the actual schematic of the BASYS 2 development board.

BASYS 2 Board Schematic
7 pages

This lecture gives an overview of the BASYS 2 development board.

Preview 04:08
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Altera Tools
3 Lectures 11:43

This is a brief overview of a few of the Altera tools available.

Altera Tools Introduction
02:11

Lecture 8 is a step by step tutorial on how to use ModelSim to simulate and verify the VHDL designs.

ModelSim VHDL Simulation Tool
05:32

A step by step tutorial on how to create a project in Quartus II and implement the design on an Altera FPGA or CPLD.

Quartus II FPGA Development Tool
04:00

This quiz is used to test your knowledge of Altera's toolset.

Altera Tools
10 questions
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Xilinx Tools
5 Lectures 20:08

A brief overview of a few of the Xilinx tools available.

Xilinx Tools Introduction
01:09

Download the Vivado Tool Suite for the BASYS 3
07:24

Here we introduces you to ISim and how to simulate your design using ISim

ISim VHDL Simulation Tool
02:13

A detailed step by step tutorial on how to use Xilinx's ISE tool to take your VHDL design and create a programming file to load onto a CPLD or FPGA.

Xilinx ISE FPGA Development Tool
07:44

This will show you how to load the FPGA programming file onto the BASYS 2 board.

Programming The BASYS 2 FPGA Development Board
01:38

This quiz will test your knowledge of the Xilinx tool set.

Xilinx Tools
10 questions
9 More Sections
About the Instructor
Jordan Christman
4.7 Average rating
935 Reviews
4,600 Students
9 Courses
Your FPGA Guy

Jordan Christman graduated from the University of Dayton with his Bachelor's degree in Electronic and Computer Engineering Technology. He also graduated from UD with his Master's degree in Electrical Engineering. Jordan currently has a patent pending for an electronic monitoring device. He has strong knowledge in FPGA (Field Programmable Gate Array) development, Digital Electronics, Circuit Board design, and VHDL design and modeling of hardware systems. Jordan's focus of study in school was embedded systems which involves circuit design, firmware development, implementation of computer hardware, and the interfacing of computer operating systems. Jordan's hobbies include mobile application development, layout and assembly of PCB's (Printed Circuit Boards), computer application programming, and anything related to electrical engineering.