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VHDL and FPGA Development for Beginners and Intermediates is a course that is designed to teach students how to create and successfully simulate their VHDL design. We will also be implementing these designs on a Xilinx BASYS 3 or BASYS 2 FPGA development board so that the students can see their designs actually running. This course starts from beginning to end in teaching the user how to turn their digital logic design into VHDL designs that can be simulated in ModelSim or ISim and then implemented on an FPGA development board. This course also covers how to use Altera's tools so students are not limited to Xilinx development boards.
This course contains over 20 lectures that will teach students the syntax and structure of VHDL. The student will be able to understand the syntax and use of specific VHDL keywords by taking this course. There are lectures included in each lab to give a background on the digital logic circuit the student will be implementing.
This course contains 7 labs that are designed so that the student will learn how to develop VHDL code. For each lab I will give the student a set of VHDL files that they will have to modify or change in order to get the project to simulate correctly in ModelSim and so they can implement the design on their FPGA board. These labs are design to help the students learn VHDL by actually coding it themselves.
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This lecture introduces this course, I will introduce myself as well as explain what will be covered in this course. The course layout is explained in this course.
Introduction to VHDL and the different ways you can use VHDL. This will give you a better understanding of what VHDL is doing and how it differentiates from a software programming language.
This lecture introduces the various data types used in the VHDL language. All of these data types are then explained more thoroughly in the later lectures.
This lecture talks about what variables, signals, and constants are and how they are used in the VHDL language.
This lecture discusses signed and unsigned data types in the VHDL language.
This lecture discusses the VHDL data types standard logic vector and standard logic.
This lecture talks about the Integer and Boolean data types in VHDL.
This lecture walks through an example VHDL file that shows various data types in VHDL being initialized.
This lecture walks through a VHDL design while talking about the various data types being used in the VHDL language.
This lecture takes students through an example VHDL design and discusses the various data types being used throughout the design.
This lecture introduces the VHDL Syntax section and explains everything that will be covered in this section.
If statements and case statements are commonly used in various programming languages. These statements are also used in VHDL and I will explain how in this lecture.
This lecture walks through and discusses how for loops and while loops are used in VHDL.
This lecture explains the differences between a for loop in VHDL verses a for loop in a software programming language such as c++.
This lecture discusses two different statements in VHDL, the when-else statement as well as the with-select-when statement.
In VHDL things happen concurrently by nature, however with the use of processes and variables we can make things happen sequentially. In this lecture I will discuss the difference between them.
This lecture walks through a VHDL design and discusses the layout and structure of the VHDL syntax.
This is a quiz that goes over the material covered in section 2 VHDL Language Basics
This lecture shows students a way they can organize their VHDL designs. As you create more designs it becomes important to organize them in a way it's easy to find and re-use your designs.
This lecture talks about the various aspects of a VHDL design and the structure of these designs.
This lecture discusses the different architecture design styles used in VHDL designs.
This lecture walks through a full adder VHDL design. this full adder design is implemented using a data flow architecture style.
This lecture walks through a full adder VHDL design. this full adder design is implemented using a behavioral architecture style.
This quiz is used to test your understanding of VHDL coding structures.
This lecture explains what a test bench is and how they are used in the VHDL language.
This lecture walks through the design of a test bench and explains the structure of a VHDL test bench.
This lecture walks through a completed test bench as an example of how a test bench is constructed.
This lecture introduces state machine in VHDL and explains how they are used.
This article explains how to design a state machine. There are various ways to design a state machine and this article covers one of them.
This article lists various FPGA development boards that students could use to complete this course. FPGA development boards not listed in this article can still be used, just message me and see if your board will work!
This is the user guide provided by digilent that explains all the different components and aspects of the BASYS 3 development board.
The schematic of the BASYS 3 development board.
An overview of the BASYS 2 FPGA development board.
This lecture contains the BASYS 2 user manual provided by digilent.
This is the actual schematic of the BASYS 2 development board.
This is a brief overview of a few of the Altera tools available.
Lecture 8 is a step by step tutorial on how to use ModelSim to simulate and verify the VHDL designs.
A step by step tutorial on how to create a project in Quartus II and implement the design on an Altera FPGA or CPLD.
This quiz is used to test your knowledge of Altera's toolset.
A brief overview of a few of the Xilinx tools available.
Here we introduces you to ISim and how to simulate your design using ISim
A detailed step by step tutorial on how to use Xilinx's ISE tool to take your VHDL design and create a programming file to load onto a CPLD or FPGA.
This will show you how to load the FPGA programming file onto the BASYS 2 board.
This quiz will test your knowledge of the Xilinx tool set.
Jordan Christman graduated from the University of Dayton with his Bachelor's degree in Electronic and Computer Engineering Technology. He also graduated from UD with his Master's degree in Electrical Engineering. Jordan currently has a patent pending for an electronic monitoring device. He has strong knowledge in FPGA (Field Programmable Gate Array) development, Digital Electronics, Circuit Board design, and VHDL design and modeling of hardware systems. Jordan's focus of study in school was embedded systems which involves circuit design, firmware development, implementation of computer hardware, and the interfacing of computer operating systems. Jordan's hobbies include mobile application development, layout and assembly of PCB's (Printed Circuit Boards), computer application programming, and anything related to electrical engineering.