Learn VHDL and FPGA Development

Learn how to create a VHDL design that can be simulated and implemented on an FPGA development board.
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  • Lectures 73
  • Length 13.5 hours
  • Skill Level All Levels
  • Languages English
  • Includes Lifetime access
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    Available on iOS and Android
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About This Course

Published 3/2015 English

Course Description

USE TIGER 10 to get this course for 10

VHDL and FPGA Development for Beginners and Intermediates is a course that is designed to teach students how to create and successfully simulate their VHDL design. We will also be implementing these designs on a Xilinx BASYS 3 or BASYS 2 FPGA development board so that the students can see their designs actually running. This course starts from beginning to end in teaching the user how to turn their digital logic design into VHDL designs that can be simulated in ModelSim or ISim and then implemented on an FPGA development board. This course also covers how to use Altera's tools so students are not limited to Xilinx development boards.

Course Structure:

This course contains over 20 lectures that will teach students the syntax and structure of VHDL. The student will be able to understand the syntax and use of specific VHDL keywords by taking this course. There are lectures included in each lab to give a background on the digital logic circuit the student will be implementing.

This course contains 7 labs that are designed so that the student will learn how to develop VHDL code. For each lab I will give the student a set of VHDL files that they will have to modify or change in order to get the project to simulate correctly in ModelSim and so they can implement the design on their FPGA board. These labs are design to help the students learn VHDL by actually coding it themselves.

Please message me before you sign up for this course!

What are the requirements?

  • Purchase a BASYS 3 or BASYS 2 FPGA Development Board
  • Download Xilinx ISE webpack, but we will cover that in this course!
  • Basic understanding of Binary Notation
  • Basic understanding of Hexadecimal Notation
  • Basic understanding of Logic Gates

What am I going to get from this course?

  • Intro to VHDL and FPGA development
  • Understand the design process for implementing a digital design onto a FPGA
  • Learn how to simulate a design in Altera’s ModelSim and Xilinx Isim
  • Learn how to use Xilinx ISE tool to program FPGA
  • Debug a VHDL design using ModelSim
  • Simulate a VHDL design using ModelSim
  • Familiarize yourself with Altera and Xilinx tools
  • Program a FPGA

What is the target audience?

  • Engineering Students
  • Engineering Managers
  • Digital Logic Enthusists
  • Individuals pursuing Electrical Engineering
  • Anyone who wants to take it for fun!

What you get with this course?

Not for you? No problem.
30 day money back guarantee.

Forever yours.
Lifetime access.

Learn on the go.
Desktop, iOS and Android.

Get rewarded.
Certificate of completion.

Curriculum

Section 1: Contact Information
Contact Information
1 page
Section 2: BASYS 3 Board
BASYS 3 Board Overview
Preview
04:42
BASYS 3 Board User Guide
19 pages
BASYS 3 Board Schematic
7 pages
Section 3: Introduction
Introduction to VHDL
Preview
14:29
Introduction to VHDL Example (same example in lecture)
03:50
Section 4: VHDL Language Basics
Data Types Part 1
16:31
Data Types Part 1 Example (same example in lecture)
05:30
Data Types Part 2
08:39
Data Types Part 2 Example (same example in lecture)
02:05
Syntax
25:23
Syntax Example 1 (same example in lecture)
07:16
Syntax Example 2 (same example in lecture)
03:04
5 questions

This is a quiz that goes over the material covered in section 2 VHDL Language Basics

Section 5: VHDL Coding Structure
VHDL Structure
08:49
VHDL Structure Example (same example in lecture)
03:09
VHDL Coding Styles
14:15
VHDL Coding Style Example 1 (same example in lecture)
02:46
VHDL Coding Style Example 2 (same example in lecture)
01:50
VHDL Coding Style Example 3 (same example in lecture)
01:50
VHDL Coding Style Example 4 (same example in lecture)
02:23
Test Benches
11:02
Test Bench Walkthrough (same example in lecture)
02:19
10 questions

This quiz is used to test your understanding of VHDL coding structures.

Section 6: Altera Tools
02:11

This is a brief overview of a few of the Altera tools available.

05:32

Lecture 8 is a step by step tutorial on how to use ModelSim to simulate and verify the VHDL designs.

04:00

A step by step tutorial on how to create a project in Quartus II and implement the design on an Altera FPGA or CPLD.

10 questions

This quiz is used to test your knowledge of Altera's toolset.

Section 7: Xilinx Tools
01:09

A brief overview of a few of the Xilinx tools available.

Download the Vivado Tool Suite for the BASYS 3
07:24
02:13

Here we introduces you to ISim and how to simulate your design using ISim

07:44

A detailed step by step tutorial on how to use Xilinx's ISE tool to take your VHDL design and create a programming file to load onto a CPLD or FPGA.

01:38

This will show you how to load the FPGA programming file onto the BASYS 2 board.

10 questions

This quiz will test your knowledge of the Xilinx tool set.

Section 8: Lab 1 - Full Adder
02:08

A introduction to the full adder.

BASYS 3 Full Adder Demonstration
14:46
01:37

This video shows a full adder implemented on a BASYS 2 board.

14:05

If you are struggling with getting the Lab 1 Demonstration to work, Lab 1 Solution is a walk through to help you complete this lab as a step-by-step guide.

Section 9: Lab 2 - Shift Register
02:17

A introduction to shift registers and their uses.

BASYS 3 Shift Register Demonstration
02:10
BASYS 2 Shift Register Demonstration
03:18
Section 10: Lab 3 - Universal Shift Register
01:48

A introduction to the universal shift register and many other shift registers.

BASYS 3 Universal Shift Register Demonstration
03:39
05:53

A demonstration showing a universal shift register implemented on the BASYS 2 board.

21:50

If you are struggling with getting the Lab 3 Demonstration to work, Lab 3 Solution is a walk through to help you complete this lab as a step-by-step guide.

Section 11: Lab 4 - 7 Segment Display
02:25

An introduction to 7 segment displays and how we will be using them in lab 4.

BASYS 3 - 7 Segment Display Demonstration
02:41
04:20

This video shows a demonstration on lab 4 running on the BASYS 2 board.

Section 12: Lab 5 - Counter
01:24

An introduction to counters in digital logic.

BASYS 3 Counter Demonstration
02:13
02:39

This video shows a counter implemented on the BASYS 2 board.

Section 13: Lab 6 - Multiplier
03:03

An introduction to how FPGA's implement multiplication.

BASYS 3 Multiplier Demonstration
04:53
BASYS 2 Multiplier Demonstration
04:46
Section 14: Lab 7 RC Servo
12:43

A quick background on RC servos and what they are used for. You will also learn what methods are used to control RC servos.

BASYS 3 RC Servo Demonstration
04:29
04:01

This is a demonstration of lab 7 implemented on the BASYS 2 board.

Section 15: BASYS 2 Board
01:48

An overview of the BASYS 2 FPGA development board.

BASYS 2 Board User Guide
12 pages
BASYS 2 Board Schematic
7 pages
BASYS 2 Board Overview
Preview
04:08
Section 16: Lecture Notes
Introduction to VHDL Notes
14 pages
Data Types Notes
20 pages
Syntax Notes
15 pages
Structure Notes
9 pages
Coding Styles Notes
10 pages
Test Benches Notes
13 pages
Altera Tools Notes
6 pages
ModelSim Notes
16 pages
Quartus II Notes
12 pages
Xilinx Tools Notes
4 pages
Isim Notes
10 pages
Xilinx ISE Project Notes
17 pages
Programming BASYS Board
5 pages
BASYS 2 Board Notes
6 pages
Section 17: Extra References
Free Range VHDL Notes
192 pages
VHDL Cookbook
111 pages

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Instructor Biography

Jordan Christman, Computer Engineer

Jordan Christman graduated from the University of Dayton with his Bachelor's degree in Electronic and Computer Engineering Technology. He also graduated from UD with his Master's degree in Electrical Engineering. Jordan currently has a patent pending for an electronic monitoring device. He has strong knowledge in FPGA (Field Programmable Gate Array) development, Digital Electronics, Circuit Board design, and VHDL design and modeling of hardware systems. Jordan's focus of study in school was embedded systems which involves circuit design, firmware development, implementation of computer hardware, and the interfacing of computer operating systems. Jordan's hobbies include mobile application development, layout and assembly of PCB's (Printed Circuit Boards), computer application programming, and anything related to electrical engineering.

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