- 20+ Years in ASIC Design and Verification and handling end to end chip design.
- Founder of VLSI Design Services company - Excel VLSI
- Extensive ASIC Design and Verification Execution Skills with hands on experience in:
o IP/Block design Verification using - Verilog, System Verilog and UVM
o VIP Development
o Code coverage and functional coverage Metrics.
o Development of test plans and randomized/methodology based test environments
o SoC Verification using C/C++
o Gate Level Simulations at chip level
o Automation scripts for tool flows.
