With over 13 years of experience in the industry, I have honed my expertise in ASIC & FPGA design, VHDL, Verilog, Scala based SpinalHDL. My proficiency extends to the functional verification of ASICs and FPGAs, where I excel in System Verilog and UVM Methodologies.

Beyond design and verification, I am skilled in a wide range of programming and scripting languages, including C/C++, Shell, Make, Python, and Perl. This versatility enables me to address complex challenges and contribute to various stages of project development. Additionally, my adeptness with databases, especially Neo4j and MySQL, allows me to efficiently manage and manipulate large data sets.

A key aspect of my career is my dedication to mentorship and knowledge sharing in the field of VLSI. I am passionate about fostering new talent and have devoted significant time to training and guiding freshers, helping them navigate and excel in this dynamic industry.