FPGA Design Learning VHDL
4.0 (19 ratings)
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FPGA Design Learning VHDL

From zero to VHDL designer. Learn how to implement your VHDL design on FPGA starting from scratch
4.0 (19 ratings)
Instead of using a simple lifetime average, Udemy calculates a course's star rating by considering a number of different factors such as the number of ratings, the age of ratings, and the likelihood of fraudulent ratings.
187 students enrolled
Created by SURF VHDL
Last updated 9/2016
English
Current price: $10 Original price: $145 Discount: 93% off
18 hours left at this price!
30-Day Money-Back Guarantee
Includes:
  • 6 hours on-demand video
  • 1 Supplemental Resource
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
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What Will I Learn?
Learn the Basic of FPGA Design
Learn VHDL Syntax
Create VHDL design through example
Debug and Simulate your VHDL design using Modelsim
Layout VHDL Design using Altera Quartus II
Test on FPGA your VHDL Design
Create a complete design on FPGA
Learn How to Implement a Seven Segment Driver
Design an UART and Connect FPGA to a PC implementing a Command Parser in VHDL
View Curriculum
Requirements
  • Basic of Boolean Algebra
  • Basic notion of FPGA and Electronics
  • Knowledge of Hex and Binary notation
  • Desire to Learn!
Description

How many times do you waste your time in finding some examples useful to resolve your VHDL problems and didn't get anything useful?

YES, it is true that we can find a lot of information for free, but not all the information we get is a good stuff. Many times we need a huge amount of time to filter good stuff from a useless material. Even if we get the information for free, we often don't think about to the time we are wasting and to the "equivalent money" we are losing wasting this time.

In Surf-VHDL, we have more than 18 years in FPGA/ASIC VHDL design.

In this course, you will learn the basic rules to implement and efficient hardware design and how to apply these rules using VHDL.

Here what you will learn at the end of the course:

  • Entity / Architecture pair definition
  • Concurrency
  • VHDL Coding Style: Structural, Behavioral, Sequential
  • Event and Transaction
  • Delay Modeling: Inertial vs Transport delay
  • Concurrent Conditional Signal Assignment
  • Understanding Driver & Source concept
  • Parametric Design: Generics
  • VHDL Types and Data object
  • VHDL Types of Data Object: Signal, Variable, Constant and FILE
  • Type bit vs ulogic vs std_logic
  • Signed and Unsigned Data Types
  • Type Conversion and Type Casting
  • Subtype definition
  • Process Statement
  • Sequential Conditional Statement: IF and CASE
  • Sequential-Iterative Statement: FOR and WHILE
  • The Assert Statement
  • Sequential WAIT Statement
  • Sensitivity List vs WAIT Statement
  • Procedure and Function
  • Packages
  • Concurrent iterative Statement FOR GENERATE
  • Concurrent conditional Statement IF GENERATE
  • TextIO package: Read/Write from file
  • Test bench design and simulation

The most important section is the LAB section. This is the real values of this course.

In the LAB section you will learn how to implement

  • Heart-bit design: let's start with a blinking led
  • Seven segment display: write a VHDL code and drive a seven segment display
  • UART: learn how to implement a UART 16650 compatible with internal FIFO
  • Command Parser: VHDL design that contains the LABs above. Connect your board to a PC and start communicate with it.

All the LABs are provided with the VHDL code that you have to complete and simulate.

In the LAB videos there will be addressed the exercise solution: you will learn how to implement the lab VHDL code, simulate and layout on FPGA

Enjoy the course and start becoming a VHDL designer!

P.S.

The course does not participate to the Udemy promo. Check on our website just clicking on the "World" icon below to be updated on our offers.



Who is the target audience?
  • If you are a Student and need a complete step by step introduction in VHDL
  • If you like Digital Design and you are looking for a complete guide to start with VHDL
  • If you need to improve your competence in FPGA Design
  • If you want to learn how to Debug and Simulate a VHDL Design
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Curriculum For This Course
Expand All 58 Lectures Collapse All 58 Lectures 05:52:10
+
Before Starting
2 Lectures 07:19

A brief introduction to the VHDL language.

Preview 03:22

Course Summary. See what you will learn following the course. Starting from VHDL language definition to implementation of a complete VHDL design into Altera Cyclone III FPGA.

Preview 03:57
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General Concept
4 Lectures 13:17

Introduction of the Entity concept

01-Entity Definition
02:44

How to define the Architecture of and Entity.

02-Entity Architecture Pair
03:49

The VHDL is a concurrent language. This means that the code you write is independent from the code position. It is hard to understand for software oriented people. Think Hardware!

03-Concurrency
03:09

Introduction to VHDL coding styles:

  • Behavioral;
  • Structural;
  • Sequential (Data Flow);
04-Coding Style
03:35
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Structural Modelling
1 Lecture 09:09

Structural Modeling is directly derived from the schematic entry. In this lesson you will understan how you can describe a schematic connection etween tuw component using VHDL

05-Structural Modeling
09:09
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Behavioral Modeling
8 Lectures 28:43

Introduction to VHDL assignment and behavioral coding style

06-Behavioral and assigment
02:02

Understand an assignemt is performed in VHDL

07-Event and Transaction
01:12

An example on how to handle behavioral modeling in VHDL

08-Behavioral Model Example
04:34

Introduction on VHDL Delay modeling type:

  • Inertial delay
  • Transport delay
09-VHDL Delay Modeling
03:33

Introduction to VHDL sequential process statement

10-Process Statement Intro
03:36

Introduction to Concurrent Conditional Signal Assignment

when clause

with sel clause

11-Concurrent Conditional Signal Assignment
06:40

How to parametrize a VHDL design. Introduction to Generic clause

12-Generics
01:11

Understanding Driver & Source concept in VHDL

13-Driver and Source
05:55
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VHDL Types
7 Lectures 23:46

Introduction to VHDL Predefined Data Types

14-Predefined DataTypes
03:06

Understand the concept of

  • signal
  • variable
  • constant
  • file

in VHDL

15-Types of Data Object
03:31

understanding the difference between the VHDL data type

  • bit and bit vector
  • standard uLogic and standard uLogic vector
  • standard logic and standard logic vector
16-bit vs ulogic vs std_logic
05:31

Introduction to VHDL User defined data type

17-VHDL User defined data type
05:35

Introduction to VHDL Signed and Unsigned data type. Introduction of numeric_std library

18-Signed Unsigned
01:16

VHDL assignment between different types. Type casting

19-Type Conversion and Casting
02:16

Introduction of VHDL Subtype and Resolution Function concept

20-Subtype
02:31
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Introduction to Modelsim
2 Lectures 14:24

Learn how to set-up a VHDL simulation using Modelsim

01 - Introduction to Modelsim
06:16

Learn how to Simulate a simple design and create a simulation script with Modelsim

Preview 08:08
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Sequential Modelling
8 Lectures 34:49

Introduction to VHDL Sequential Modeling coding style

21-Sequential Modeling
02:54

Introduction to the sequential conditional statement:

  • if then else
  • case
22-Sequential Conditional Statement
03:22

Introduction to VHDL Sequential Iteration Statement :

  1. For Loop
  2. While Loop
23-Sequential Iteration Statement
06:59

Introduction to VHDL Assert Behavioral Statement. This statement is useful during behavioral model simulation to report on screen simulation messages

24-Assert Statement
04:18

Introduction to Wait Statement. Learn the equivalence between sensitivity list and wait statement in a VHDL process

25-Sensitivity List vs Wait Statement
01:42

Learn how to use wait statement in a VHDL process

26-Wait Statement
04:20

Learn how to use subprogram Procedure and Function in VHDL

27-Subprogram
08:06

Learn how to create a user defined library package

28-Packages
03:08
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Concurrent Iterative Statement
1 Lecture 10:24

Introduction to the concurrent generate statement:

  • For-generate
  • if-generate
29-Generate Statement
10:24
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TextIO
1 Lecture 03:56

Introduction on TextIO VHDL library. Learn how to access to a file in VHDL and how to implemnt an efficient simulation and verification strategy

Introduction to TextIO library
03:56
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BONUS
2 Lectures 13:25

Example on how to read from file in VHDL

Bonus1-Test bench Read Form File
10:04

Bonus1-Test bench Write to File

Bonus2-Test bench Write to File
03:21
5 More Sections
About the Instructor
SURF VHDL
3.2 Average rating
103 Reviews
2,936 Students
2 Courses
The Easiest Way to Learn VHDL

We want to support FPGA/ASIC junior and, why not, senior hardware designers in finding examples and useful hints for their VHDL designs.

Our target is to enable you to “surf” the VHDL:

We made the VHDL learning experience as simple as it can be.

We are sharing with you everything that actually helped ourselves in mastering the VHDL.

We strongly believe in knowledge sharing as one of the most important means to improve this world.

We would very much appreciate your cooperation either by submitting your questions or by sharing the link to this website with friends and colleagues

Enjoy the experience!