FPGA Design Learning VHDL

From zero to VHDL designer. Learn how to implement your VHDL design on FPGA starting from scratch
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Instructed by SURF VHDL IT & Software / Hardware
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  • Lectures 58
  • Length 6 hours
  • Skill Level Intermediate Level
  • Languages English
  • Includes Lifetime access
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About This Course

Published 12/2015 English

Course Description

How many times do you waste your time in finding some examples useful to resolve your VHDL problems and didn't get anything useful?

YES, it is true that we can find a lot of information for free, but not all the information we get is a good stuff. Many times we need a huge amount of time to filter good stuff from a useless material. Even if we get the information for free, we often don't think about to the time we are wasting and to the "equivalent money" we are losing wasting this time.

In Surf-VHDL, we have more than 18 years in FPGA/ASIC VHDL design.

In this course, you will learn the basic rules to implement and efficient hardware design and how to apply these rules using VHDL.

Here what you will learn at the end of the course:

  • Entity / Architecture pair definition
  • Concurrency
  • VHDL Coding Style: Structural, Behavioral, Sequential
  • Event and Transaction
  • Delay Modeling: Inertial vs Transport delay
  • Concurrent Conditional Signal Assignment
  • Understanding Driver & Source concept
  • Parametric Design: Generics
  • VHDL Types and Data object
  • VHDL Types of Data Object: Signal, Variable, Constant and FILE
  • Type bit vs ulogic vs std_logic
  • Signed and Unsigned Data Types
  • Type Conversion and Type Casting
  • Subtype definition
  • Process Statement
  • Sequential Conditional Statement: IF and CASE
  • Sequential-Iterative Statement: FOR and WHILE
  • The Assert Statement
  • Sequential WAIT Statement
  • Sensitivity List vs WAIT Statement
  • Procedure and Function
  • Packages
  • Concurrent iterative Statement FOR GENERATE
  • Concurrent conditional Statement IF GENERATE
  • TextIO package: Read/Write from file
  • Test bench design and simulation

The most important section is the LAB section. This is the real values of this course.

In the LAB section you will learn how to implement

  • Heart-bit design: let's start with a blinking led
  • Seven segment display: write a VHDL code and drive a seven segment display
  • UART: learn how to implement a UART 16650 compatible with internal FIFO
  • Command Parser: VHDL design that contains the LABs above. Connect your board to a PC and start communicate with it.

All the LABs are provided with the VHDL code that you have to complete and simulate.

In the LAB videos there will be addressed the exercise solution: you will learn how to implement the lab VHDL code, simulate and layout on FPGA

Enjoy the course and start becoming a VHDL designer!

P.S.

The course does not participate to the Udemy promo. Check on our website just clicking on the "World" icon below to be updated on our offers.



What are the requirements?

  • Basic of Boolean Algebra
  • Basic notion of FPGA and Electronics
  • Knowledge of Hex and Binary notation
  • Desire to Learn!

What am I going to get from this course?

  • Learn the Basic of FPGA Design
  • Learn VHDL Syntax
  • Create VHDL design through example
  • Debug and Simulate your VHDL design using Modelsim
  • Layout VHDL Design using Altera Quartus II
  • Test on FPGA your VHDL Design
  • Create a complete design on FPGA
  • Learn How to Implement a Seven Segment Driver
  • Design an UART and Connect FPGA to a PC implementing a Command Parser in VHDL

What is the target audience?

  • If you are a Student and need a complete step by step introduction in VHDL
  • If you like Digital Design and you are looking for a complete guide to start with VHDL
  • If you need to improve your competence in FPGA Design
  • If you want to learn how to Debug and Simulate a VHDL Design

What you get with this course?

Not for you? No problem.
30 day money back guarantee.

Forever yours.
Lifetime access.

Learn on the go.
Desktop, iOS and Android.

Get rewarded.
Certificate of completion.

Curriculum

Section 1: Before Starting
03:22

A brief introduction to the VHDL language.

03:57

Course Summary. See what you will learn following the course. Starting from VHDL language definition to implementation of a complete VHDL design into Altera Cyclone III FPGA.

Section 2: General Concept
02:44

Introduction of the Entity concept

03:49

How to define the Architecture of and Entity.

03:09

The VHDL is a concurrent language. This means that the code you write is independent from the code position. It is hard to understand for software oriented people. Think Hardware!

03:35

Introduction to VHDL coding styles:

  • Behavioral;
  • Structural;
  • Sequential (Data Flow);
Section 3: Structural Modelling
09:09

Structural Modeling is directly derived from the schematic entry. In this lesson you will understan how you can describe a schematic connection etween tuw component using VHDL

Section 4: Behavioral Modeling
02:02

Introduction to VHDL assignment and behavioral coding style

01:12

Understand an assignemt is performed in VHDL

04:34

An example on how to handle behavioral modeling in VHDL

03:33

Introduction on VHDL Delay modeling type:

  • Inertial delay
  • Transport delay
03:36

Introduction to VHDL sequential process statement

06:40

Introduction to Concurrent Conditional Signal Assignment

when clause

with sel clause

01:11

How to parametrize a VHDL design. Introduction to Generic clause

05:55

Understanding Driver & Source concept in VHDL

Section 5: VHDL Types
03:06

Introduction to VHDL Predefined Data Types

03:31

Understand the concept of

  • signal
  • variable
  • constant
  • file

in VHDL

05:31

understanding the difference between the VHDL data type

  • bit and bit vector
  • standard uLogic and standard uLogic vector
  • standard logic and standard logic vector
05:35

Introduction to VHDL User defined data type

01:16

Introduction to VHDL Signed and Unsigned data type. Introduction of numeric_std library

02:16

VHDL assignment between different types. Type casting

02:31

Introduction of VHDL Subtype and Resolution Function concept

Section 6: Introduction to Modelsim
06:16

Learn how to set-up a VHDL simulation using Modelsim

08:08

Learn how to Simulate a simple design and create a simulation script with Modelsim

Section 7: Sequential Modelling
02:54

Introduction to VHDL Sequential Modeling coding style

03:22

Introduction to the sequential conditional statement:

  • if then else
  • case
06:59

Introduction to VHDL Sequential Iteration Statement :

  1. For Loop
  2. While Loop
04:18

Introduction to VHDL Assert Behavioral Statement. This statement is useful during behavioral model simulation to report on screen simulation messages

01:42

Introduction to Wait Statement. Learn the equivalence between sensitivity list and wait statement in a VHDL process

04:20

Learn how to use wait statement in a VHDL process

08:06

Learn how to use subprogram Procedure and Function in VHDL

03:08

Learn how to create a user defined library package

Section 8: Concurrent Iterative Statement
10:24

Introduction to the concurrent generate statement:

  • For-generate
  • if-generate
Section 9: TextIO
03:56

Introduction on TextIO VHDL library. Learn how to access to a file in VHDL and how to implemnt an efficient simulation and verification strategy

Section 10: BONUS
10:04

Example on how to read from file in VHDL

03:21

Bonus1-Test bench Write to File

Section 11: LAB Heart-Bit
07:46

The LAB will introduce you into a simple VHDL design. You have to design and code a module that shall blink a led with programmable duty cycle.

09:07

ing ModelsimSimulate your Heart-Bit LAb us

05:52

Layout the Heart-Bit VHDL code and test using Altera DE0 board

Section 12: LAB Seven Segment
07:14

Learn how to design a seven segment driver in VHDL

07:41

Simulate a part of VHDL code: edge-detector

05:07

Layout the seven segment driver VHDL code on Altera DE0 board using Quartus II

Section 13: LAB on UART
06:25

UART LAB Description. You will undestand how to implement a UART 115200-8-N-1 in VHDL RTL

13:01

Learn how to implement the VHDL code for an UART

10:09

Simulate and debug your UART VHDL RTL code using Modelsim

02:40

You must create a FIFO component in order to use UART. In this lesson you will learn how to create a FIFO macro using Altera Quartus II

17:00

Now you are ready to test your UART design using Altera DE0 Board. Layout the VHDL design on FPGA, connect the board to a PC and communicate using an hyperterminal

Section 14: LAB Command Parser
10:31

Understand the command parser concept and how to implement the design

03:39

Understand the command parser control logic

01:09

Understand how to implement the Lab

14:23

Simulate and Debug your code using Modelsim

05:06

Layout the Command Parser VHDL design on DE0 Altera Board using Altera Quartus II

06:12

Test the command parser design. Connect the PC to the board and communicate with it!

Section 15: BONUS - How to Implement Your First FPGA Design Using VHDL
12:58

In this video, you will learn the basic rules for a good VHDL design.

These rules can be applied to all design methodology not only in VHDL design.

You can follow this approach in all your design (C/C++, java, php, etc).

Start learning how to implement in VHDL an 8-bit counter and seven segment display controller.

15:19

In this second video, you will learn how to implement VHDL test bench for your design and start to simulate it using ModelSim.

At the end of the video you will be able to setup a VHDL test bench, simulate it and create ModelSim simulation script

12:12

After VHDL Design and Simulation is the time to Layout the VHDL code on FPGA. In this video you will learn how to create a complete Quartus II project, Layout the VHDL code on FPGA, setup the pin-out and create Quartus II script file. During the VHDL design test you will find a problem…

18:27

In the previous video lessons, you did learn how to implement a VHDL good design strategy, Simulate the VHDL design using ModelSim, Layout VHDL code on Altera DE0 board FPGA Test the VHDL design. During the test you did find a problem: when you use an external FPGA pin to increment the counter you get fake pulse. Now is the time to understand how to fix the problem directly into the VHDL code.

1 page

Instruction to download the VHDL code for LAB

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Instructor Biography

SURF VHDL, The Easiest Way to Learn VHDL

We want to support FPGA/ASIC junior and, why not, senior hardware designers in finding examples and useful hints for their VHDL designs.

Our target is to enable you to “surf” the VHDL:

We made the VHDL learning experience as simple as it can be.

We are sharing with you everything that actually helped ourselves in mastering the VHDL.

We strongly believe in knowledge sharing as one of the most important means to improve this world.

We would very much appreciate your cooperation either by submitting your questions or by sharing the link to this website with friends and colleagues

Enjoy the experience!

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