FPGA Design Learning VHDL
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FPGA Design Learning VHDL

From zero to VHDL designer. Learn how to implement your VHDL design on FPGA starting from scratch
4.5 (32 ratings)
Instead of using a simple lifetime average, Udemy calculates a course's star rating by considering a number of different factors such as the number of ratings, the age of ratings, and the likelihood of fraudulent ratings.
298 students enrolled
Created by SURF VHDL
Last updated 7/2017
Current price: $12 Original price: $145 Discount: 92% off
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  • 6 hours on-demand video
  • 2 Supplemental Resources
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion

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What Will I Learn?
  • Learn the Basic of FPGA Design
  • Learn VHDL Syntax
  • Create VHDL design through example
  • Debug and Simulate your VHDL design using Modelsim
  • Layout VHDL Design using Altera Quartus II
  • Test on FPGA your VHDL Design
  • Create a complete design on FPGA
  • Learn How to Implement a Seven Segment Driver
  • Design an UART and Connect FPGA to a PC implementing a Command Parser in VHDL
View Curriculum
  • Basic of Boolean Algebra
  • Basic notion of FPGA and Electronics
  • Knowledge of Hex and Binary notation
  • Desire to Learn!

How many times do you waste your time in finding some examples useful to resolve your VHDL problems and didn't get anything useful?

YES, it is true that we can find a lot of information for free, but not all the information we get is a good stuff. Many times we need a huge amount of time to filter good stuff from a useless material. Even if we get the information for free, we often don't think about to the time we are wasting and to the "equivalent money" we are losing wasting this time.

In Surf-VHDL, we have more than 18 years in FPGA/ASIC VHDL design.

In this course, you will learn the basic rules to implement and efficient hardware design and how to apply these rules using VHDL.

Here what you will learn at the end of the course:

  • Entity / Architecture pair definition
  • Concurrency
  • VHDL Coding Style: Structural, Behavioral, Sequential
  • Event and Transaction
  • Delay Modeling: Inertial vs Transport delay
  • Concurrent Conditional Signal Assignment
  • Understanding Driver & Source concept
  • Parametric Design: Generics
  • VHDL Types and Data object
  • VHDL Types of Data Object: Signal, Variable, Constant and FILE
  • Type bit vs ulogic vs std_logic
  • Signed and Unsigned Data Types
  • Type Conversion and Type Casting
  • Subtype definition
  • Process Statement
  • Sequential Conditional Statement: IF and CASE
  • Sequential-Iterative Statement: FOR and WHILE
  • The Assert Statement
  • Sequential WAIT Statement
  • Sensitivity List vs WAIT Statement
  • Procedure and Function
  • Packages
  • Concurrent iterative Statement FOR GENERATE
  • Concurrent conditional Statement IF GENERATE
  • TextIO package: Read/Write from file
  • Test bench design and simulation

The most important section is the LAB section. This is the real values of this course.

In the LAB section you will learn how to implement

  • Heart-bit design: let's start with a blinking led
  • Seven segment display: write a VHDL code and drive a seven segment display
  • UART: learn how to implement a UART 16650 compatible with internal FIFO
  • Command Parser: VHDL design that contains the LABs above. Connect your board to a PC and start communicate with it.

All the LABs are provided with the VHDL code that you have to complete and simulate.

In the LAB videos there will be addressed the exercise solution: you will learn how to implement the lab VHDL code, simulate and layout on FPGA

Enjoy the course and start becoming a VHDL designer!


The course does not participate to the Udemy promo. Check on our website just clicking on the "World" icon below to be updated on our offers.

Who is the target audience?
  • If you are a Student and need a complete step by step introduction in VHDL
  • If you like Digital Design and you are looking for a complete guide to start with VHDL
  • If you need to improve your competence in FPGA Design
  • If you want to learn how to Debug and Simulate a VHDL Design
Compare to Other FPGA Courses
Curriculum For This Course
58 Lectures
Before Starting
2 Lectures 07:19

A brief introduction to the VHDL language.

Preview 03:22

Course Summary. See what you will learn following the course. Starting from VHDL language definition to implementation of a complete VHDL design into Altera Cyclone III FPGA.

Preview 03:57
General Concept
4 Lectures 13:17

Introduction of the Entity concept

01-Entity Definition

How to define the Architecture of and Entity.

02-Entity Architecture Pair

The VHDL is a concurrent language. This means that the code you write is independent from the code position. It is hard to understand for software oriented people. Think Hardware!


Introduction to VHDL coding styles:

  • Behavioral;
  • Structural;
  • Sequential (Data Flow);
04-Coding Style
Structural Modelling
1 Lecture 09:09

Structural Modeling is directly derived from the schematic entry. In this lesson you will understan how you can describe a schematic connection etween tuw component using VHDL

05-Structural Modeling
Behavioral Modeling
8 Lectures 28:43

Introduction to VHDL assignment and behavioral coding style

06-Behavioral and assigment

Understand an assignemt is performed in VHDL

07-Event and Transaction

An example on how to handle behavioral modeling in VHDL

08-Behavioral Model Example

Introduction on VHDL Delay modeling type:

  • Inertial delay
  • Transport delay
09-VHDL Delay Modeling

Introduction to VHDL sequential process statement

10-Process Statement Intro

Introduction to Concurrent Conditional Signal Assignment

when clause

with sel clause

11-Concurrent Conditional Signal Assignment

How to parametrize a VHDL design. Introduction to Generic clause


Understanding Driver & Source concept in VHDL

13-Driver and Source
VHDL Types
7 Lectures 23:46

Introduction to VHDL Predefined Data Types

14-Predefined DataTypes

Understand the concept of

  • signal
  • variable
  • constant
  • file


15-Types of Data Object

understanding the difference between the VHDL data type

  • bit and bit vector
  • standard uLogic and standard uLogic vector
  • standard logic and standard logic vector
16-bit vs ulogic vs std_logic

Introduction to VHDL User defined data type

17-VHDL User defined data type

Introduction to VHDL Signed and Unsigned data type. Introduction of numeric_std library

18-Signed Unsigned

VHDL assignment between different types. Type casting

19-Type Conversion and Casting

Introduction of VHDL Subtype and Resolution Function concept

Introduction to Modelsim
2 Lectures 14:24

Learn how to set-up a VHDL simulation using Modelsim

01 - Introduction to Modelsim

Learn how to Simulate a simple design and create a simulation script with Modelsim

Preview 08:08
Sequential Modelling
8 Lectures 34:49

Introduction to VHDL Sequential Modeling coding style

21-Sequential Modeling

Introduction to the sequential conditional statement:

  • if then else
  • case
22-Sequential Conditional Statement

Introduction to VHDL Sequential Iteration Statement :

  1. For Loop
  2. While Loop
23-Sequential Iteration Statement

Introduction to VHDL Assert Behavioral Statement. This statement is useful during behavioral model simulation to report on screen simulation messages

24-Assert Statement

Introduction to Wait Statement. Learn the equivalence between sensitivity list and wait statement in a VHDL process

25-Sensitivity List vs Wait Statement

Learn how to use wait statement in a VHDL process

26-Wait Statement

Learn how to use subprogram Procedure and Function in VHDL


Learn how to create a user defined library package

Concurrent Iterative Statement
1 Lecture 10:24

Introduction to the concurrent generate statement:

  • For-generate
  • if-generate
29-Generate Statement
1 Lecture 03:56

Introduction on TextIO VHDL library. Learn how to access to a file in VHDL and how to implemnt an efficient simulation and verification strategy

Introduction to TextIO library
2 Lectures 13:25

Example on how to read from file in VHDL

Bonus1-Test bench Read Form File

Bonus1-Test bench Write to File

Bonus2-Test bench Write to File
5 More Sections
About the Instructor
4.6 Average rating
121 Reviews
3,121 Students
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The Easiest Way to Learn VHDL

We want to support FPGA/ASIC junior and, why not, senior hardware designers in finding examples and useful hints for their VHDL designs.

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