Professional Summary :

I am an experienced educator and VLSI professional with a strong background in digital design and semiconductor industry practices. With hands-on exposure to standard cell characterization, synthesis, STA, physical design, and Verilog RTL design, along with years of academic teaching experience, I bring a unique perspective that connects theory with real-world VLSI applications. My passion lies in simplifying complex concepts so learners can master both educational fundamentals and industry-ready skills.

Subjects Taught:

Computer Organization and Architecture (COA) – ECE

Analog Electronics (AE) – EEE (Teaching Methodology focus)

Digital System Design using Verilog HDL – Theory & Lab

Database Management Systems – Lab

Digital Electronics

Projects Guided / Executed :

SoC Floorplan Constrained Design (picorv32a) – Physical Design (Synopsys ICC2)

Design and Analysis of Mealy Finite State Machine for 4-bit Sequence (Design Compiler, PrimeTime)

Design and Synthesis Comparison of Multiple Adder Architectures (Cadence Genus)

Design and Analysis of Multipliers Using Adder Topologies (Xilinx ISE, Nexys 4 DDR)

Design and Performance Comparison Among Various Adder Topologies (Xilinx Vivado, Nexys 4 DDR)

Standard Cell Library Design & Development using 180nm & 90nm Technology Nodes (Cadence Liberate, Spectre, Virtuoso, Library Compiler)

Design of Efficient VLSI Arithmetic Circuits

Design and Performance Comparison among Various Adder Topologies (Academic Project)

Industry Experience :

Worked in the VLSI industry with experience in:

Standard Cell Characterization using Cadence Liberate and Synopsys tools.

RTL Design in Verilog and Integration into Synthesis Flows.

Synthesis and Static Timing Analysis (STA) for ASIC designs.

Physical Design (PD), including floorplanning, placement, CTS, and routing.

Applied EDA toolchains (Cadence & Synopsys) across the RTL-to-GDSII flow in real-world projects.

Achievements:

Qualified GATE Examination

College Topper in B.E. (Electronics and Communication Engineering)

College Topper in M.E. (Embedded Systems and VLSI Design)