I teach Verilog HDL and RTL design the way I wish I had learned it: by typing, simulating, and reading real logs—not by memorizing slides.

I built RTLStudio, a browser IDE where you lint, simulate, and synthesize Verilog without installing CAD tools. My free Verilog Class is 30 short lessons: Docs, a TODO, Run, waveform, and Yosys, filmed inside the same lab you can open yourself.

I focus on beginners and working engineers who need synthesizable habits—wire vs reg, always blocks, FSMs, and clean testbenches—so you can practice every day and actually finish a path from Hello World to hardware patterns.