VSD - Timing ECO (engineering change order) webinar
4.2 (32 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
226 students enrolled

VSD - Timing ECO (engineering change order) webinar

Let's design better chips
4.2 (32 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
226 students enrolled
Created by Kunal Ghosh
Last updated 2/2018
English
English [Auto-generated]
Current price: $11.99 Original price: $94.99 Discount: 87% off
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This course includes
  • 1.5 hours on-demand video
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
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What you'll learn
  • Design better chips
  • Analyze designs, from power, performance and area perspective, altogether

Requirements
  • You should have completed STA-1, STA-2 and Physical Design course atleast 50%
  • You should understand basic timing analogies like setup time and hold time
Description

First, let’s define better? Better in terms of Power. Performance and Area

Every VLSI engineer, an RTL architect, or Lead Synthesis Engineer, or Senior Physical Designer, or Director of Signoff timing analysis – practically everyone is doing timing ECO at every step of their flow. I, being a part of Signoff timing analysis and Physical Design world, am doing ECO almost every day, and so I understood that its more than adding buffer and up-sizing/downsizing cells.

All of the factors or ways shown in above image impacts either dynamic power or short-circuit power or leakage power. The question is, do you know why do we still do it? Do you know how can we still do with minimally impact on other parameters? Yes, No, Don’t Know….

It’s time to unveil more than 9 strategies to do timing ECO and below are few of them 

  1. Routing congestion aware timing ECO
  2. Path based analysis ECO for selected endpoints
  3. Replicated modules based timing ECO
  4. Legalized timing ECO
  5. Margin based timing ECO

…..and many more…

See, I told you, timing ECO is more than just adding buffers and sizing cells…Do you want to know all the strategies?
Do you want to be a better timing engineer? Engineering includes tons of changes and modifications from inception to final product. Hence its called Engineering Change Order (ECO)

Welcome all of you to my "Timing ECO webinar", which was conducted along with ~50people on 6th Jan, 2018. Join and re-live the webinar. 

Who this course is for:
  • Anyone who wants to understand timing ECO strategies and how it impacts overall chip PPA (power, performance, area)
  • Anyone who wants to be called as "Signoff Timing Expert", rather than, "Signoff Timing Engineer"
Course content
Expand all 13 lectures 01:42:23
+ Power, performance and area
4 lectures 35:23
Factors impacting dynamic and short-circuit power
09:59
Impact of add_buffer and sizing on performance and area
09:35
Impact of load and Vt swap on performance and area
07:43
+ ECO Strategies - Margin based and slack based fixing for selective end points
3 lectures 27:56
Margin based DRV and setup-hold fixing
10:55
Selective end-point based fixing with margin and slack range
06:14
Slack based and number of path based fixing
10:47
+ PBA fixing and leakage ECO
2 lectures 13:54
PBA (path-based analysis) based and reg2reg based fixing
06:42
+ Hierarchical and Physical aware ECO
2 lectures 18:25
Hierarchical ECO with top only hierarchical only and full chip ECO strategy
09:50
Physical aware ECO
08:35
+ Conclusion
1 lecture 02:21
Bottle-neck analysis and conclusion
02:21