VSD - Timing ECO (engineering change order) webinar

Let's design better chips

Highest Rated

Created byKunal Ghosh

Last updated 2/2018

English

English [Auto],

What you'll learn

Design better chips
Analyze designs, from power, performance and area perspective, altogether

Course content

6 sections • 13 lectures • 1h 42m total length

Introduction4:24
Explore timing ECO concepts, from behavioral descriptions to digital gate-level design, floorplanning, placement, and clock synthesis, culminating in static timing analysis and optimization for power and performance.

Factors impacting dynamic and short-circuit power9:59
Explore factors affecting dynamic power and short-circuit power in digital circuits, including cv squared energy during switching, the impact of adding or deleting cells, and transition time on short-circuit currents.
Factors impacting short-circuit and leakage power8:06
Explore how input and output capacitances influence short-circuit current and leakage power during switching, and how threshold voltage and process variations affect voltage transfer and area-performance tradeoffs.
Impact of add_buffer and sizing on performance and area9:35
Explores how adding buffers and resizing them impacts performance, area, and timing slack in digital circuits, including upsizing and downsizing tradeoffs and short-circuit power.
Impact of load and Vt swap on performance and area7:43
Explore how load and Vt swap affect circuit performance and area, and how buffer trees redistribute fan-out to improve timing, with trade-offs in dynamic, short-circuit, and leakage power.

Margin based DRV and setup-hold fixing10:55
Apply margin based fixing to timing ECO, fixing setup and hold by adjusting max capacitance and max transition, upsizing selective cells and trimming layouts to meet picosecond and slack targets.
Selective end-point based fixing with margin and slack range6:14
Learn selective end-point based fixing with margin and slack range to fix only selected pots, balancing performance improvement with limited area impact.
Slack based and number of path based fixing10:47
Master slack-based fixing and max pots techniques to control timing in engineering change orders. Learn set up targets, DMX select, and how pot counts influence fixed results.

PBA (path-based analysis) based and reg2reg based fixing6:42
Explore path-based analysis (PBA) based fixing and reg2reg based fixing for timing ECO changes, comparing how each targets slack and worst-case paths, and their up-sizing trade-offs.
Leakage recovery ECO strategy7:12
Analyze leakage recovery strategies in timing ECOs, comparing cell-level and flop-level fixes, and balance slack and clock skew through deliberate sequencing to protect performance.

Hierarchical ECO with top only hierarchical only and full chip ECO strategy9:50
Explore hierarchical eco strategies, including top-only and full-chip approaches, to fix timing slack at the interface or inside blocks by upsizing cells and applying fixes for replicated head blocks.
Physical aware ECO8:35
Learn how physical aware ECO improves predictability by integrating physical changes with existing timing strategies, using strategically placed buffers to fix timing without new routing, and addressing legalization concerns.

Requirements

You should have completed STA-1, STA-2 and Physical Design course atleast 50%
You should understand basic timing analogies like setup time and hold time

Description

First, let’s define better? Better in terms of Power. Performance and Area

Every VLSI engineer, an RTL architect, or Lead Synthesis Engineer, or Senior Physical Designer, or Director of Signoff timing analysis – practically everyone is doing timing ECO at every step of their flow. I, being a part of Signoff timing analysis and Physical Design world, am doing ECO almost every day, and so I understood that its more than adding buffer and up-sizing/downsizing cells.

All of the factors or ways shown in above image impacts either dynamic power or short-circuit power or leakage power. The question is, do you know why do we still do it? Do you know how can we still do with minimally impact on other parameters? Yes, No, Don’t Know….

It’s time to unveil more than 9 strategies to do timing ECO and below are few of them

Routing congestion aware timing ECO
Path based analysis ECO for selected endpoints
Replicated modules based timing ECO
Legalized timing ECO
Margin based timing ECO

…..and many more…

See, I told you, timing ECO is more than just adding buffers and sizing cells…Do you want to know all the strategies?
Do you want to be a better timing engineer? Engineering includes tons of changes and modifications from inception to final product. Hence its called Engineering Change Order (ECO)

Welcome all of you to my "Timing ECO webinar", which was conducted along with ~50people on 6th Jan, 2018. Join and re-live the webinar.

Who this course is for:

Anyone who wants to understand timing ECO strategies and how it impacts overall chip PPA (power, performance, area)
Anyone who wants to be called as "Signoff Timing Expert", rather than, "Signoff Timing Engineer"

VSD - Timing ECO (engineering change order) webinar

What you'll learn

Explore related topics

Course content

Introduction1 lecture • 4min

Power, performance and area4 lectures • 35min

ECO Strategies - Margin based and slack based fixing for selective end points3 lectures • 28min

PBA fixing and leakage ECO2 lectures • 14min

Hierarchical and Physical aware ECO2 lectures • 18min

Conclusion1 lecture • 2min

Requirements

Description

Who this course is for: