VSD - TCL programming - From novice to expert - Part 1
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VSD - TCL programming - From novice to expert - Part 1

The Expert In Anything Was Once A Beginner
4.2 (33 ratings)
Instead of using a simple lifetime average, Udemy calculates a course's star rating by considering a number of different factors such as the number of ratings, the age of ratings, and the likelihood of fraudulent ratings.
256 students enrolled
Created by Kunal Ghosh
Last updated 7/2017
English
Curiosity Sale
Current price: $10 Original price: $95 Discount: 89% off
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Includes:
  • 4.5 hours on-demand video
  • 1 Article
  • 5 Supplemental Resources
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
What Will I Learn?
  • Build TCL scripts on their own from scratch
  • Build their own UI (user-interface)
  • Build their own procs and commands
View Curriculum
Requirements
  • You should be able to understand basic UNIX commands like vim, ls -ltr, etc.
  • You should have a virtual machine with UNIX and TCL running, if using a Windows laptop
  • You should be able to install any linux package
Description

And I really believe in that...

I was a novice in TCL programming 10 years back. One thing that led from novice to an expert is "Practice"

Be it learning scripting language or an EDA tool, nothing beats 'concepts'. I have been proving this in my courses, how learning a tool is the last 5% task of entire learning flow.

My students, who have been working with on several projects and also learning through my courses, have not only learned semiconductors, but lived the journey. And I promise, the same will happen with my this course on TCL scripting as well.

I have been using the same approach in last 10 years for solving problems, be it a TCL script issue or an issue with STA timing violation or an issue with DRC or an issue with floor planning or an issue with routing congestion, you name it..

You will witness the same in all my courses and in this one as well. Let's unveil the concepts of data flow and manipulation using TCL scripts

Who is the target audience?
  • Anyone who wants to do TCL programming
  • Anyone who wants to learn basic programming algorithm and data flow
  • Anyone who wants to code
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Curriculum For This Course
29 Lectures
04:14:39
+
Introduction
2 Lectures 14:53

Introduction to sub-task
09:06
+
Sub-Task One : VSDSYNTH Toolbox usage scenarios
2 Lectures 19:33
Scenario 1 - User doesn't provides input csv file
09:52

+
Sub-Task Two - From CSV to format[1] and SDC - Variable Creation
7 Lectures 59:47
Various tasks involved in format conversion
08:17

openMSP430_design_details.csv
00:02

Auto-Create variables using matrix and arrays
10:12

Initialize variables for auto-creation variables task
11:39


Auto creation of variables complete
09:51

Variable Creation DEMO using TCL
08:56
+
Sub-Task Two - From CSV to format[1] and SDC - Processing constraints,csv
4 Lectures 38:29
Checking existence of files and folders mentioned in design_details.csv
10:23

Convert constraints.csv file to a matrix object
09:44

Compute row number using complex matrix proccessing
10:06

+
Sub-Task Two - From CSV to format[1] and SDC - Processing clock constraints
5 Lectures 43:46
Algorithm to identify column number for clock latency constraints
08:18

Start writing clock latency constraints in SDC file
09:42

Complete clock latency constraints and clock slew constraints in SDC file
09:08

Code to create clock constraints with clock period and duty cycle
09:47

DEMO for creating complete clock constraints
06:51
+
Sub-Task Two - From CSV to format[1] and SDC - Processing input constraints
8 Lectures 01:12:52
Introduction to task of differentiating between bits and bus
07:58

Algorithm to categorize input ports as bits and bussed
09:10

File access and pattern creation steps
08:29

Regular expression and regular substitute to get fixed space strings
08:39

Demo for grepping input ports from all verilogs and reformatting for fixed space
11:05

Read, split, uniquify, sort and join input ports to remove duplication
09:39

Evaluate length of string and Demo of bits/bussed differentiation script
10:02

Demo for input constraints generation and bits/bussed differentiation
07:50
+
Full script for download and Conclusion
1 Lecture 05:19
Constraints generation logic for output port and Conclusion!!
05:19
About the Instructor
Kunal Ghosh
4.3 Average rating
1,717 Reviews
12,681 Students
14 Courses
Digital and Sign-off expert at VLSI System Design(VSD)

I received MTech Degree in Department of Electrical Engineering (EE) from Indian Institute of Technology (IIT) Bombay in 2010 and specialized in VLSI Design & Nanotechnology during my 3-year tenure at IIT Bombay, from 2007 - 2010.

Corporate Life @

1) Lead Physical design and STA engineer, Qualcomm, Bangalore India, 07/2010-04/2013

2) Lead Sales Application engineer, Cadence Design systems, Bangalore India, 04/2013-01/17

Hands on with Technology @

1) MSM (mobile station mode chips) - MSM chips are used for CDMA modulation/demodulation. It consists of DSP’s and microprocessors for running applications such as web-browsing, video conferencing, multimedia services, etc.

2) Memory test chips - Memory test chips are used to validate functionality of 28nm custom/compiler memory as well as characterize their timing, power and yield.

3) DDR-PHY test chips - DDR-PHY test chips are basically tested for high speed data transfer

4) Timing and physical design Flow development for 130nm MOSFET technology node till 16nm FinFET technology node.

5) “IR aware STAandLow power STA

6) Analyzed STA engine behavior for design size up to 850 million instance count

ACADEMIC

1) Research Assistant to Prof. Richard Pinto and Prof. Anil Kottantharayil on “Sub-100nm optimization using Electron Beam Lithography”, which intended to optimize RAITH-150TWO Electron Beam Lithography tool and the process conditions to attain minimum resolution, use the mix-and-match capabilities of the tool for sub-100nm MOSFET fabrication and generate mask plates for feature sizes above 500nm.

2) Research Assistant to with Prof. Madhav Desai, to characterize RTL, generated from C-to-RTL AHIR compiler, in terms of power, performance and area. This was done by passing RTL, generated from AHIR compiler, through standard ASIC tool chain like synthesis and place & route. The resulting netlist out of PNR was characterized using standard software

PUBLICATION 

1) “A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems” submitted in the conference “13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France

2) Concurrent + Distributed MMMC STA for 'N' views

3) Signoff Timing and Leakage Optimization On 18M Instance Count Design With 8000 Clocks and Replicated Modules Using Master Clone Methodology With EDI Cockpit

4) Placement-aware ECO Methodology - No Slacking on Slack

Online Presence - Courses on Udemy

Now, to be really successful in the field of VLSI and Semiconductors, you need to take the courses in below order:

1) VSD - Physical design flow

2) VSD - Clock tree synthesis - Part 1 & 2

3) VSD - Signal Integrity

4) VSD - Static timing analysis - Part 1 & 2 (Can be taken in between)

5) VSD - Circuit design and SPICE simulations Part 1 & Part 2 (This is the core of VLSI, so you can take it in beginning or end)

6) VLSI - Essential concepts and detailed interview guide (This course is a glimpse of all above courses, but for details of each topic, you need to take course 1) to 5).)

7) VSD - Custom Layout (Can be taken in between) 

8) VSD - Library characterization and modelling - Part 1 (STA-1 and 2, Circuit design and SPICE simulations-1 and 2 are mandatory)

Connect with me for more guidance !!

Hope you enjoy the session best of luck for future !!