VSD - TCL programming - From novice to expert - Part 2
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VSD - TCL programming - From novice to expert - Part 2

The Conclusion
3.7 (5 ratings)
Instead of using a simple lifetime average, Udemy calculates a course's star rating by considering a number of different factors such as the number of ratings, the age of ratings, and the likelihood of fraudulent ratings.
104 students enrolled
Created by Kunal Ghosh
Last updated 9/2017
Current price: $10 Original price: $95 Discount: 89% off
5 hours left at this price!
30-Day Money-Back Guarantee
  • 37 mins on-demand video
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
What Will I Learn?
  • Build TCL scripts on their own from scratch
  • Build their own UI (user-interface)
  • Build their own procs and commands
View Curriculum
  • TCL Programming - Part 1 needs to completed atleast 50%
  • Yosys synthesis tool needs to be installed

As promised, again, TCL Programming - Part 2 course has been pre-launched with 5 videos. Many more to come, as always. 

This course is a unique mixture of TCL programming being used in manipulating output EDA tools, creating EDA commands (like call_timer, read_sdc, and many more) and generating output timing summary report. The concept of this course can be extended to create any command, moreover, create any kind of UI you wish to.

Certain per-requisites are necessary for this course i.e. you need to complete TCL programming - Part 1 course, atleast 50% to enjoy this course to the fullest. As with my other courses, I am very sure, this course will also be one of "Best-Sellers". 

I can guarantee you, this time, your ride with this course will be more memorable one, as its a "first-of-its-kind" "state-of-the-art" unique blending of TCL with EDA. So ride along, and enjoy while learning. More videos are on its way, stay tuned....

Who is the target audience?
  • Anyone who wishes to build his/her UI and learn TCL programming from basics
  • Anyone who wants to learn basics of RTL synthesis
  • Anyone who wants to learn basic programming algorithm and data flow
Compare to Other Tcl Courses
Curriculum For This Course
1 Lecture 03:01
Introduction to Yosys synthesis tool usage
4 Lectures 33:51
Example of a memory module RTL description

Memory functionality and Synthesis using Yosys

Memory Read operation discussed in detail
About the Instructor
Kunal Ghosh
4.4 Average rating
1,904 Reviews
13,280 Students
15 Courses
Digital and Sign-off expert at VLSI System Design(VSD)

I received MTech Degree in Department of Electrical Engineering (EE) from Indian Institute of Technology (IIT) Bombay in 2010 and specialized in VLSI Design & Nanotechnology during my 3-year tenure at IIT Bombay, from 2007 - 2010.

Corporate Life @

1) Lead Physical design and STA engineer, Qualcomm, Bangalore India, 07/2010-04/2013

2) Lead Sales Application engineer, Cadence Design systems, Bangalore India, 04/2013-01/17

Hands on with Technology @

1) MSM (mobile station mode chips) - MSM chips are used for CDMA modulation/demodulation. It consists of DSP’s and microprocessors for running applications such as web-browsing, video conferencing, multimedia services, etc.

2) Memory test chips - Memory test chips are used to validate functionality of 28nm custom/compiler memory as well as characterize their timing, power and yield.

3) DDR-PHY test chips - DDR-PHY test chips are basically tested for high speed data transfer

4) Timing and physical design Flow development for 130nm MOSFET technology node till 16nm FinFET technology node.

5) “IR aware STAandLow power STA

6) Analyzed STA engine behavior for design size up to 850 million instance count


1) Research Assistant to Prof. Richard Pinto and Prof. Anil Kottantharayil on “Sub-100nm optimization using Electron Beam Lithography”, which intended to optimize RAITH-150TWO Electron Beam Lithography tool and the process conditions to attain minimum resolution, use the mix-and-match capabilities of the tool for sub-100nm MOSFET fabrication and generate mask plates for feature sizes above 500nm.

2) Research Assistant to with Prof. Madhav Desai, to characterize RTL, generated from C-to-RTL AHIR compiler, in terms of power, performance and area. This was done by passing RTL, generated from AHIR compiler, through standard ASIC tool chain like synthesis and place & route. The resulting netlist out of PNR was characterized using standard software


1) “A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems” submitted in the conference “13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France

2) Concurrent + Distributed MMMC STA for 'N' views

3) Signoff Timing and Leakage Optimization On 18M Instance Count Design With 8000 Clocks and Replicated Modules Using Master Clone Methodology With EDI Cockpit

4) Placement-aware ECO Methodology - No Slacking on Slack

Online Presence - Courses on Udemy

Now, to be really successful in the field of VLSI and Semiconductors, you need to take the courses in below order:

1) VSD - Physical design flow

2) VSD - Clock tree synthesis - Part 1 & 2

3) VSD - Signal Integrity

4) VSD - Static timing analysis - Part 1 & 2 (Can be taken in between)

5) VSD - Circuit design and SPICE simulations Part 1 & Part 2 (This is the core of VLSI, so you can take it in beginning or end)

6) VLSI - Essential concepts and detailed interview guide (This course is a glimpse of all above courses, but for details of each topic, you need to take course 1) to 5).)

7) VSD - Custom Layout (Can be taken in between) 

8) VSD - Library characterization and modelling - Part 1 (STA-1 and 2, Circuit design and SPICE simulations-1 and 2 are mandatory)

Connect with me for more guidance !!

Hope you enjoy the session best of luck for future !!