VSD - Static Timing Analysis (STA) Webinar
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VSD - Static Timing Analysis (STA) Webinar

Characterize your design performance LIVE with me, just the way the industry works
4.4 (7 ratings)
Instead of using a simple lifetime average, Udemy calculates a course's star rating by considering a number of different factors such as the number of ratings, the age of ratings, and the likelihood of fraudulent ratings.
80 students enrolled
Created by Kunal Ghosh
Last updated 5/2017
English
Curiosity Sale
Current price: $10 Original price: $95 Discount: 89% off
30-Day Money-Back Guarantee
Includes:
  • 2.5 hours on-demand video
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
What Will I Learn?
  • Entire STA flow and ECO flow
  • Explore ideas and ways to implement automated ECO flow
  • Calculate performance of your design, just the way industry works, and may be, get a feel of working in a semi-conductor industry
View Curriculum
Requirements
  • Basics of Static Timing Analysis, not mandatory, as it will be anyways covered in this webinar
  • Basics of digital gates and flip-flops
Description

This time .... Its more personal

You have been very supportive for all these 6 years and I would like to "Thank You" from the bottom of my heart Now its time to enter your hearts and minds, so we connect for lifetime.

The reason for the success of my webinars and workshops was the connection that you had with me, and, believe me, that's tough to build. It would not have been possible without you believing in me and my product....

So here I bring the entire webinar ONLINE for you..

We had conducted 4 workshops and 2 webinars on STA in Bangalore, India, where designers and students from Chicago, Minnesota, New York and San-Francisco connected LIVE with me. The webinar was very interactive and couple of mind-blowing ideas and queries came up.

Everyone who attended the webinar and workshops, and myself, ended up with the same feeling....this webinar should go LIVE online so that everyone, including the attendees of my webinar, can re-live the entire experience again and again. 

So, I bring this to you. Its LIVE. Its ONE-2-ONE and Its more Personal Coaching as you would see more of interaction rather than one-sided talking. Grab your seat and enjoy the similar experience that we had...

Stay Tuned....

Who is the target audience?
  • Everyone who's interested in working on LIVE designs using open-source STA tool
  • Everyone who want to know what's the structure of this industry, specially STA
  • Everyone who would love to explore ways to innovate using open-source tools
  • Everyone looking to work with me on LIVE project
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Curriculum For This Course
16 Lectures
02:23:23
+
Start Here
1 Lecture 05:20
+
IC design components
4 Lectures 39:50
RTL, floor-planning and power-planning
08:43

Placement and Clock tree synthesis
08:41

Introduction to static timing analysis (STA)
10:57

STA detailing
11:29
+
Runtime theory and demo
2 Lectures 15:58
Design size, RAM and runtime relationship
06:00

Runtime check demo using Opentimer
09:58
+
Design speed and performance characterization
4 Lectures 40:46
Worst negative slack (WNS) and total negative slack (TNS)
10:05

Introduction to term 'performance' and 'clock constraints'
10:04

IO constraints
10:49

+
Timing libraries and engineering change order(ECO)
4 Lectures 35:18
Brief description of timing libraries
09:24

Brief description about driver model and receiver model
08:29

Useful tips for operating frequency calculation
07:34

Hold ECO detailed steps with LIVE demo
09:51
+
Conclusion
1 Lecture 06:11
Assignment description and conclusion
06:11
About the Instructor
Kunal Ghosh
4.3 Average rating
1,717 Reviews
12,672 Students
14 Courses
Digital and Sign-off expert at VLSI System Design(VSD)

I received MTech Degree in Department of Electrical Engineering (EE) from Indian Institute of Technology (IIT) Bombay in 2010 and specialized in VLSI Design & Nanotechnology during my 3-year tenure at IIT Bombay, from 2007 - 2010.

Corporate Life @

1) Lead Physical design and STA engineer, Qualcomm, Bangalore India, 07/2010-04/2013

2) Lead Sales Application engineer, Cadence Design systems, Bangalore India, 04/2013-01/17

Hands on with Technology @

1) MSM (mobile station mode chips) - MSM chips are used for CDMA modulation/demodulation. It consists of DSP’s and microprocessors for running applications such as web-browsing, video conferencing, multimedia services, etc.

2) Memory test chips - Memory test chips are used to validate functionality of 28nm custom/compiler memory as well as characterize their timing, power and yield.

3) DDR-PHY test chips - DDR-PHY test chips are basically tested for high speed data transfer

4) Timing and physical design Flow development for 130nm MOSFET technology node till 16nm FinFET technology node.

5) “IR aware STAandLow power STA

6) Analyzed STA engine behavior for design size up to 850 million instance count

ACADEMIC

1) Research Assistant to Prof. Richard Pinto and Prof. Anil Kottantharayil on “Sub-100nm optimization using Electron Beam Lithography”, which intended to optimize RAITH-150TWO Electron Beam Lithography tool and the process conditions to attain minimum resolution, use the mix-and-match capabilities of the tool for sub-100nm MOSFET fabrication and generate mask plates for feature sizes above 500nm.

2) Research Assistant to with Prof. Madhav Desai, to characterize RTL, generated from C-to-RTL AHIR compiler, in terms of power, performance and area. This was done by passing RTL, generated from AHIR compiler, through standard ASIC tool chain like synthesis and place & route. The resulting netlist out of PNR was characterized using standard software

PUBLICATION 

1) “A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems” submitted in the conference “13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France

2) Concurrent + Distributed MMMC STA for 'N' views

3) Signoff Timing and Leakage Optimization On 18M Instance Count Design With 8000 Clocks and Replicated Modules Using Master Clone Methodology With EDI Cockpit

4) Placement-aware ECO Methodology - No Slacking on Slack

Online Presence - Courses on Udemy

Now, to be really successful in the field of VLSI and Semiconductors, you need to take the courses in below order:

1) VSD - Physical design flow

2) VSD - Clock tree synthesis - Part 1 & 2

3) VSD - Signal Integrity

4) VSD - Static timing analysis - Part 1 & 2 (Can be taken in between)

5) VSD - Circuit design and SPICE simulations Part 1 & Part 2 (This is the core of VLSI, so you can take it in beginning or end)

6) VLSI - Essential concepts and detailed interview guide (This course is a glimpse of all above courses, but for details of each topic, you need to take course 1) to 5).)

7) VSD - Custom Layout (Can be taken in between) 

8) VSD - Library characterization and modelling - Part 1 (STA-1 and 2, Circuit design and SPICE simulations-1 and 2 are mandatory)

Connect with me for more guidance !!

Hope you enjoy the session best of luck for future !!