VSD - SoC Design of the PicoRV32 RISCV micro-processor

Join this hands-on webinar to learn how to build a complete SoC reference design around the PicoRV32 microprocessor, from floorplanning and placement to routing, netlisting, and validating with open-source tools.

Discover how the efabless platform combines open-source design tools with real foundry processes, enabling cloud-based digital synthesis, placement, routing, DRC, and verification for SoC design.

Join a live Q&A to log in to the Efabless marketplace, use Flow and Cloud V, and explore a community-driven design marketplace with design requests and knowledge base tutorials.

Cloud V enables exploring soft, hard, and Verilog IP in a managed workflow, from adding soft IP to pushing to the cloud, with Raven SBI and open vs closed options.

Select the Raven SBI as the top level module, synthesize for a target foundry process in open galaxy, then export the verilog netlist and review standard cells and area.

import a synthesized verilog netlist into open galaxy, assign the target foundry process, and create a new project using the project manager and GUI.

Navigate the open Galaxie system back-end flow by selecting the ravan sbi project, then run preparation, synthesis, and post-processing before placement, routing, and timing analysis.

Navigate the pin arrangement UI and automatic grouping of vectors to optimize a PicoRV32 layout, using default synthesis flow insights and groupings to simplify border placement and wiring.

Master pin placement and floor planning for SoC design by grouping signals, assigning pins to the top, bottom, and left, and using a simulated annealing placement algorithm.

participate in a live q&a on placement and static timing analysis for the VSD SoC PicoRV32 design, covering pin mapping, maximum frequency, and log-file troubleshooting.

Route post-route STA and LVS check to ensure no fail routes, assess density effects on routing, generate parasitics, and validate netlist and layout migration with DRC and LDS.

Master debugging LVS and DRC for the PicoRV32 SoC by editing netlists, using magic shortcut keys, and tracing shorts and mismatches to fix the layout.

Explore a live q&a on lvs and fixing drc, rotating vias to reduce metal overhang, correcting notch spacing, and using magic painting to repair violations quickly.

Perform live drc cleanups by fixing metal notches, inside corners, and via rotation, using a standard cell set and magic commands; verify drc zero and save your progress.

Discusses DRC and net discrepancies, compares manual and automated routing with Magic, and proposes provisional catalog uploads to accelerate efabless and qflow designs while preserving certification through design review.

Create a full chip project and design a pad frame for floorplanning and integration. Manage catalog entries, hierarchy, and power routing, then validate layout with a Verilog netlist.

Open the library manager, select the SPI block from the compatible library, place it in the layout, and choose pad sets (3.3-volt outer, 1.8-volt core) while consulting the PTF view.

Select cells from the library, copy pads, and arrange a pad frame with corner, input, output, power, and ground pads; rotate and distribute them for a four-sided package.

Move and align pads to form a DRC clean pad frame using keypad navigation, zoom, and hierarchy in the design tools, while addressing DRC errors caused by abstract tabs.

Route the reset signal from the core to the pad using top-level routing, pad-frame with ESD diodes and clamps, and interactive tools to wire across metal layers.

Route signals with the wiring tool and shift right mouse button to connect pins like csb and sdi via contacts; then verify with drc and lds checks for clean routing.

Explore dynamic power estimation and power routing for a pico rv32 soc, covering power planning, bus width and pitch, IR drop, and multi-bus strategies for raven-scale cores.

Tie down unused inputs, reinforce ground and power buses, add substrate contacts, and insert antenna diodes to mitigate antenna violations during chip verification.

Label every pin on the layout, attach sticky metal-one labels, assign port numbers, and verify with LVS; review netlists and Verilog integration to ensure chip passes.

Design a simple frequency divider chip using open source tools, synthesize in Open Galaxy, export, verify, add pad frame, and submit for certification to earn a badge and conference presentation.

Conclude the PicoRV32 SoC design journey by examining physical design from placement to fabrication, highlighting challenges, open submissions, and achieving a working chip on the public platform.