VSD - RTL Synthesis Q&A Webinar
3.7 (3 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
50 students enrolled

VSD - RTL Synthesis Q&A Webinar

Here are the answers, you were looking for....
3.7 (3 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
50 students enrolled
Created by Kunal Ghosh
Last updated 5/2018
English
English [Auto-generated]
Current price: $11.99 Original price: $194.99 Discount: 94% off
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This course includes
  • 1.5 hours on-demand video
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
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What you'll learn
  • Students will get structured answers to queries which they might otherwise find difficult to search online
  • Perception about synthesis and opensource tools will change

  • Students and professionals from other fields will be excited to choose Synthesis as their full-time career as so many things are yet to explore

Requirements
  • Knowledge of Yosys is nice to have, but not required
  • Digital design knowledge is needed
  • Knowledge of synthesis and physical design flow is essential
Description

Welcome to first ever QnA webinar on RTL synthesis using Yosys. This webinar was conducted on 19th May, 2018 with Clifford Wolf

Its a Q&A webinar on RTL Synthesis, by Clifford Wolf. Clifford is architect of Yosys which is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.

Clifford will be answering 23 queries on RTL synthesis. TOP23 query submissions are directly eligible for certificates from our company VSD Corp. Pvt. Ltd.

Note of Appreciation I have worked with Clifford in my course on TCL programming Part 1 & 2, and really Thank him for all his guidance for making of TCL programming course.

Clifford has more than 20+ years of experience and is been known the Architect and Father of Yosys, OpenSCAD (now maintained by Marius Kintel), SPL (a not very popular scripting language), EmbedVM (a very simple compiler+vm for 8 bit micros), Lib(X)SVF (a library to play SVF/XSVF files over JTAG), ROCK Linux (discontinued since 2010)

All the best and happy learning.

Who this course is for:
  • Anyone who wants to enter VLSI front-end design field should take this course, as this course will answer lot of questions related to synthesis in general
  • Anyone looking to start using opensource tool Yosys for synthesis
  • Anyone curious to know what's happening in the world of RTL synthesis
Course content
Expand 11 lectures 01:37:31
+ Introduction
11 lectures 01:37:31
Queries next stage RTL design, HDL and asynchronous logic synthesis answered
07:40
Query on best way to do synthesis answered
11:04
Queries on ideal clock, synthesis challenges across nodes and multiple clock
09:07
Queries on partitioning, power estimation and power efficient RTL answered
09:27
Queries on testbench for maximum coverage and physical aware Yosys answered
10:21
Yosys project start-up story answered
12:06
Queries on machine learning in Yosys, handling scan logic and derates answered
10:45
Queries on next milestones of Yosys and fsm_recode command answered
10:19
Query on equivalence check and conclusion
05:53