VSD - RTL Synthesis Q&A Webinar

Here are the answers, you were looking for....

Created byKunal Ghosh

Last updated 5/2018

English

English [Auto],

What you'll learn

Students will get structured answers to queries which they might otherwise find difficult to search online
Perception about synthesis and opensource tools will change
Students and professionals from other fields will be excited to choose Synthesis as their full-time career as so many things are yet to explore

Course content

1 section • 11 lectures • 1h 37m total length

Introduction2:56
Join this introduction to rtl synthesis in a live q&a webinar, where participants' questions drive discussions on rtl synthesis concepts, tools, and practical insights.
Queries next stage RTL design, HDL and asynchronous logic synthesis answered7:40
Explore the next stage of RTL design and HDL synthesis by using C/C++ high level synthesis tools, understanding compilers and asynchronous logic challenges, clockless designs, and debugging aids.
Query on best way to do synthesis answered11:04
Explore timing-driven synthesis and static timing analysis for rtl design, using ABC for clock estimate and discussing Open HLS options and practical synthesis decisions.
Queries on ideal clock, synthesis challenges across nodes and multiple clock9:07
Investigate ideal clock concepts, synthesis challenges across nodes and multiple clocks, and how memory resources, retiming, and domain crossing impact RTL synthesis decisions.
Queries on synopsys lib file reading and synthesis constraints answered7:53
Explore how to read synopsys lib files and apply synthesis constraints using open-source tools, mapping liberty files to logic gates and handling timing-driven cases.
Queries on partitioning, power estimation and power efficient RTL answered9:27
Learn partitioning strategies for RTL on FPGA, compare design hierarchy with flattening, use black boxes and cell instances, and address power estimation and power-efficient RTL synthesis.
Queries on testbench for maximum coverage and physical aware Yosys answered10:21
Explore test bench coverage concepts, including functional and code coverage, and discuss timing driven synthesis with physical aware yosys, abc, and formal methods for design validation.
Yosys project start-up story answered12:06
Discover how a student built a small-subset rtl synthesis tool as open source, using test cases and user-driven goals to grow broader capabilities.
Queries on machine learning in Yosys, handling scan logic and derates answered10:45
Explore how machine learning augments yosys in rtl synthesis and formal verification, including constraints handling, a classifier to predict outcomes, scan chain considerations, and timing derates in abc.
Queries on next milestones of Yosys and fsm_recode command answered10:19
Explore next milestones for Yosys and the fsm_recode command, and learn how FSM encoding, one-hot options, and formal verification strategies improve synthesis.
Query on equivalence check and conclusion5:53
Equivalence checks verify RTL correctness across synthesis tools, quickly expose bugs in synthesis flows, and clarify ambiguous constructs like parallel case attributes to ensure reliable FPGA synthesis.

Requirements

Knowledge of Yosys is nice to have, but not required
Digital design knowledge is needed
Knowledge of synthesis and physical design flow is essential

Description

Welcome to first ever QnA webinar on RTL synthesis using Yosys. This webinar was conducted on 19th May, 2018 with Clifford Wolf

Its a Q&A webinar on RTL Synthesis, by Clifford Wolf. Clifford is architect of Yosys which is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.

Clifford will be answering 23 queries on RTL synthesis. TOP23 query submissions are directly eligible for certificates from our company VSD Corp. Pvt. Ltd.

Note of Appreciation I have worked with Clifford in my course on TCL programming Part 1 & 2, and really Thank him for all his guidance for making of TCL programming course.

Clifford has more than 20+ years of experience and is been known the Architect and Father of Yosys, OpenSCAD (now maintained by Marius Kintel), SPL (a not very popular scripting language), EmbedVM (a very simple compiler+vm for 8 bit micros), Lib(X)SVF (a library to play SVF/XSVF files over JTAG), ROCK Linux (discontinued since 2010)

All the best and happy learning.

Who this course is for:

Anyone who wants to enter VLSI front-end design field should take this course, as this course will answer lot of questions related to synthesis in general
Anyone looking to start using opensource tool Yosys for synthesis
Anyone curious to know what's happening in the world of RTL synthesis