VSD - RISCV : Instruction Set Architecture (ISA) - Part 1b

Explain signed addition and overflow for a 4-bit word in RISCV ISA, using two's complement and matrix mapping to illustrate overflow conditions.

Derives overflow conditions for signed addition using a sign-matrix, explains sign bits and two's complement representations, and demonstrates overflow detection with an assembly language program for an ALU.

Explore how a RISC-V signed addition overflow check works by tracing an overflow condition through registers, conditional branches, and R-type instructions.

Explore how signed subtraction for 4-bit words is performed with addition hardware, using one's complement of B and addition to illustrate overflow behavior.

Analyze signed subtraction overflow using a quadrant matrix to identify overflow regions and implement signals in assembly language with conditional branches.

Demonstrates a 4-bit multiplication algorithm using multiplicand and multiplier, with add-and-shift steps, register-based flowchart, and a counter-driven loop to compute the product.

Explain how RISC-V mul and mulh produce a 128-bit product from two 64-bit operands, storing high bits in edge and low bits in middle for unsigned multipliers.

Demonstrates binary division in a 64-bit hardware context, showing how to initialize the remainder and divisor registers, the left half of the divisor, and compute the quotient and remainder.

Explore the division algorithm in the RISC-V ISA, using ones complement subtraction and adding one to form negatives, handling remainder, and performing left shifts and counter-driven iterations.

Explore the division algorithm in RISCV ISA, detailing how the quotient and remainder are computed with the remainder register, divisor shifts, and signed versus unsigned flow.

Explore how to express decimal and binary numbers using normalized scientific notation, with examples involving decimal points, signs, and binary expansion.

Explore the IEEE 754 floating point standard, covering single and double precision, sign and exponent bits, and fraction representation in RV64 architectures.

Explore how floating point representation handles zeros, infinities, NaNs, and denormalized numbers, and how exponent bias and sign bits influence comparisons and sorting in RISCV ISA.

Explore biased floating point representation and how bias affects exponent interpretation. Learn how normalization and subnormal numbers define the smallest and largest representable values, including zero and not-a-number cases.

Explain how the floating-point standard uses bias and exponent to represent numbers, with normalization and fraction bits, and compare single versus double precision while outlining the addition algorithm.

Develop a decimal floating-point addition algorithm by assigning exponent and significant digits, aligning exponents, normalizing the result, and handling overflow, underflow, and rounding.

Explore binary floating-point addition, including extracting signs, exponents, and significands, aligning exponents, performing significand addition, normalization, and the impact of RV64D’s larger significand bits on precision versus RV64F.

Develop a decimal floating-point multiplication algorithm, compute biased exponents, multiply significands, then normalize and adjust the result, converting between decimal and binary for clarity.

Demonstrate binary floating-point multiplication for rv64d, covering decimal-to-binary conversion, normalization, exponent adjustment, and significand multiplication under isa constraints.