VSD - Physical Design Webinar using EDA tool 'Proton'
3.9 (34 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
214 students enrolled

VSD - Physical Design Webinar using EDA tool 'Proton'

I call this 'freedom of EDA tools'
3.9 (34 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
214 students enrolled
Last updated 1/2018
English
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Current price: $11.99 Original price: $94.99 Discount: 87% off
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This course includes
  • 3.5 hours on-demand video
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
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What you'll learn
  • Build, Verify and PNR any design, for which you have an RTL
  • Characterize any post-layout design in terms of frequency, net count, instance count, runtime and many more

  • Do entire floorplanning of chip online using steps mentioned in webinar

Requirements
  • You should have completed Physical design course on Udemy
  • You should have completed STA-1 course on Udemy
Description

Be it in any field - Change is inevitable. Let’s change the way we used to do Physical design. This time, no need to install tools on laptop, no licenses needed, no hidden costs, just your gmail login id and you are ready to design your first chip online. Find it hard to believe? 

I welcome you to my first “Physical Design” Webinar that happened on 20th Jan 2018 at 9am IST. This is 3-hour action-packed webinar with myself being the host and below 3 people from industry

Rajeev Srivastava -

Rajeev is technical advisor to webchip and also was one of the developers of Proton while at Silverline Inc. Currently he is a Sr Principal Physical Design Engineer at NXP.  While at Silverline, he was a expert user of Proton and has worked with customers to use proton successfully on many chip design projects. He will be helping with the webinar today and show how to run the tools and also answer proton related questions.

Aditya Pratap -

Aditya is the main developer and chief architect of Webchip.He was also one of the main developers of open source EDA tool proton that we will see in action today in our webinar.

Sanjeev Gupta -

Sanjeev is an VLSI & System design expert and also chief of operations at webchip.

Finally one word - 'LIVE' - pin placement, verification and routing on WEB. All with zero license fee using industry grade EDA tool. That's innovation. This is something which has never happened before.

Learn from the best, and expect a shift in your professional thinking.

I will see you all in webinar and happy learning

Who this course is for:
  • Anyone who wants to learn chip designing using industry grade EDA tool
  • Anyone who has the limitation of tool installation and wants to design chip online
Course content
Expand all 23 lectures 03:30:11
+ RTL Design functionality verification and view physical cells
4 lectures 38:19
Multiplier functionality description
07:41
Functionality verification using iverilog on 'Proton'
11:24
LIVE Q&A with participants regarding LEF
09:59
+ RTL Synthesis steps and Q&A
3 lectures 27:06
Synthesis using 'qflow yosys'
09:43
Pre-layout timing analysis and LIVE QnA
06:43
+ Floorplanning and power planning strategies
3 lectures 32:00
Floorplanning concept and demonstration
10:29
Detail discussion on power and gnd rails location
10:48
LIVE QnA with participants regarding power planning
10:43
+ Placement and Routing steps using 'Proton'
5 lectures 44:47
Cell and automated pin placement concept and demo using graywolf
05:46
LIVE QnA with participants regarding cell and pin placement
09:03
More LIVE QnA on flylines and demo routing step
10:13
Commands to analyze and report routing statistics
09:30
+ Post layout STA and future work
4 lectures 39:26
Post layout timing analysis steps and discussion on new feature enablement
09:57
LIVE QnA discussion with participants regarding timing ECO
09:36
Plan going further and future tentative tool enhancements
12:04