VSD - Making the Raven chip: How to design a RISC-V SoC

Explore the raven chip design flow for a RISC-V-based system on a chip, from platform overview and cloning a project to risk five, peripherals, verification, and layout for foundry readiness.

Explore open source tools and cloud-based design for IP on the efabless platform, featuring open galaxy, a marketplace, and single sign-on via verified link.

Explore the efabless platform in this introductory interactive tutorial to design a raven chip for a RISC-V SoC, using the IP catalog, try hard IP, and create demos.

Learn to push IP, such as a level shifter, into your Open Galaxy account by creating a demo project, syncing your library, and pushing the item to Open Galaxy.

Set pvt conditions and simulate a level shifter with the characterization tool, producing a single-run typical 110 degrees result to verify ip blocks and understand min/max delays.

Delve into how the efabless platform characterizes designs from schematic capture to extracted characterization and netlists, compares layouts, and interprets graphs like propagation delay versus supply voltage.

Familiarize yourself with Verilog, basic C, and the Linux command line. Understand PicoRV32 RV32 IMC, memory-mapped design, and simple peripherals like UART and flash.

present raven soc overview, contrasting it with fpga-based memory blocks and detailing external foundry sram, internal register file, on-chip address decoding, interrupt routing, and 180-nm clocking.

Join a live Q&A on Raven full chip design, exploring crystal oscillator, PLL timing, 20 MHz input clocks, and the bandgap 1.2V reference with a test bench.

Clone the Raven chip into the Open Galaxy environment and clone the IP, pulling dependencies from libraries into your projects. Synchronize dependencies and push to Open Galaxy to complete integration.

Clone the Raven chip and explore open galaxies design space. Parameterize the pic Arvina 32 core inside the Raven soc wrapper, and connect clock, reset, memory, and the flash controller.

Develop a digital uart and an independent sbi module to control pll, crystal oscillator, master reset, and the 1.8 volt regulator for safe testing of the raven chip.

Explore how Raven Verilog top level instantiates every submodule, uses behavioral SRAM and real valued Verilog for analog peripherals, and models pad frames with 3.3V and 1.8V logic for simulation.

Explore voltage domains in a RISC-V SoC, including 1.8-volt and 3.3-volt with decoupling caps, and learn level shifting down and up with standard cells and a serial programmable interface.

Explore design choices for a general-purpose test-chip SoC with analog and digital I/O, SBI controls, Arduino/Raspberry Pi inspiration, and QFN packaging at a 0.18 μm sweet spot.

Design an on-chip analog routing and calibration using a bandgap reference to calibrate the ADC, plus memory-mapped GPO and GPIO, with multiplexers enabling real-time monitoring and interrupts.

Experience a live q&a on Raven chip design goals and components, exploring packaging, foundry collaboration, nodes from 180 to 45 nm, transistor-level and analog design, and power and timing reports.

Explore how the memory map controls everything outside SRAM by declaring control bits and decoding a 32-bit address space to route reads and writes to GPO and SRAM.

Explore the SoC memory map, including SRAM overlay on flash SBI, program start, stack pointer, and top-level connections, with voltage-domain aware level shifting and analog blocks.

Explore a sparse 32-bit memory map where each address maps a single bit to control GPOs and ADCs, with C test benches and Verilog wrappers guided by a Makefile.

Examine the Raven chip boot code that zeros registers and loops, and dissect the C and Verilog testbenches, clocks, and SBI flash integration for rapid testing.

Explore an interactive Raven testbench workflow, compiling and simulating a full Raven suite with GPO, ADC, DAC, and SPI through makefiles, GCC, hex creation, and GTKWave.

Follow this interactive tutorial to set up and make a new Raven testbench, configuring Verilog components and a top-level Makefile to test the DAC, bandgap, and GPO output.

Run and debug the Raven chip testbench by enabling the bandgap, setting the analog outputs, and routing the comparator to the GPO; use GTKWave to inspect waveforms.

Improve live testbench debugging and reconfiguring by fixing verilog wiring for the DAC and multiplexer, then verify analog and digital signals in waveform simulations.

Explore design flow from Verilog validation to layout and fabrication, including VHDL considerations, then tackle a weeklong raven sock timer design with clock multiplexing, memory map, test bench, and submission.

Conclude the Raven chip webinar by reviewing synthesis progress, tool fixes, and future sessions on analog IP, open-source hardware, and designing a RISC-V SoC.