VLSI - Essential concepts and detailed interview guide
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VLSI - Essential concepts and detailed interview guide

VLSI Academy
Bestselling
4.1 (417 ratings)
Instead of using a simple lifetime average, Udemy calculates a course's star rating by considering a number of different factors such as the number of ratings, the age of ratings, and the likelihood of fraudulent ratings.
9,551 students enrolled
Created by Kunal Ghosh
Last updated 3/2015
English
Current price: $10 Original price: $195 Discount: 95% off
5 hours left at this price!
30-Day Money-Back Guarantee
Includes:
  • 11.5 hours on-demand video
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
What Will I Learn?
  • To bridge the gap between Understanding and Application of Knowledge, this leads to innovation
View Curriculum
Requirements
  • Individuals having Basic Knowledge of Electrical and Electronics
Description

This course is about Basic concepts of VLSI System Design. The course is designed in the form of micro-videos, which delivers content in the form of Info-Graphics. It is designed for self-learning and will help to polish the Industrial skills in VLSI World. This course will cover end-to-end description from basic Device Physics to Chip Design.The introductory video series focuses on the basic elemental physics and electrical characteristics of MOS Transistor.
Do visit our website: www.vlsisystemdesign.com...
Learn Advance VLSI Concepts in Our New Video Series
@ https://www.udemy.com/vlsi-academy-clock-tree-synthesis/

Who is the target audience?
  • Individuals keen to learn about VLSI and Chip World
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Curriculum For This Course
72 Lectures
11:20:53
+
Physical Design Flow Overview
4 Lectures 39:17

Netlist Binding And Placement Optimization
09:34

Clock Net Shielding
09:34

Route - DRC Clean - Parasitics Extraction - Final STA
09:33
+
Floorplanning
4 Lectures 38:37
Utilization Factor And Aspect Ratio
09:10

Concept of Pre-placed Cells
09:27

Power Planning
10:26

Pin Placement And Logical Cell Placement Blockage
09:34
+
Placement
3 Lectures 28:12
Netlist Binding And Placement
09:22

Optimize Placement Using Estimated Wire Length And Capacitance
10:02

Optimize Placement Continued
08:48
+
Timing Analysis With Ideal Clocks
4 Lectures 37:00
Setup Time Analysis And Introduction To Flip-Flop Setup Time
09:44

Setup Timing Analysis With Multiple Clocks
08:49

Multiple Clock Timing Analysis And Introduction To Data Slew Check
09:06

Data Slew Check
09:21
+
Clock Tree Synthesis - Introduction And Quality Check Parameters
5 Lectures 49:00
Introduction To Clock Tree Synthesis
10:05

Duty Cycle And Latency Check
10:15

Latency And Power Check
10:20

Power And Crosstalk Quality Check
10:46

Glitch Quality Check
07:34
+
H-Tree
3 Lectures 29:30
H-Tree Algorithm And Skew Check
09:41

H-Tree Pulse Width And Duty Cycle Check
09:51

H-Tree Latency And Power Check
09:58
+
Clock Tree Modelling and Observations
3 Lectures 28:51
Clock Tree Modelling
09:26

Clock Tree Building
09:58

Clock Tree Observations
09:27
+
Buffered H-Tree
5 Lectures 50:44
H-Tree Buffering Observations
11:06

H-Tree Pulse Width Check And Issues With Regular Buffers
09:13

CMOS Inverter PMOS/NMOS Matching Switching Resistance Solution
09:51

H-Tree Clock Buffers And Pulse Width Check
10:48

Dynamic Power And Short Circuit Power
09:46
+
Clock Tree Optimization Checklist
3 Lectures 26:07
Optimization Checklist
09:48

Leakage Current Reduction Technique
09:35

Optimized Clock Tree Power And Latency Check
06:44
+
Static Timing Analysis With Real Clocks
3 Lectures 31:07
Static Timing Analysis With Real Clocks
09:48

Impact Of Unbalanced Skew On Setup Time
10:00

Impact Of Unbalanced Skew On Hold Time
11:19
10 More Sections
About the Instructor
Kunal Ghosh
4.3 Average rating
1,708 Reviews
12,630 Students
14 Courses
Digital and Sign-off expert at VLSI System Design(VSD)

I received MTech Degree in Department of Electrical Engineering (EE) from Indian Institute of Technology (IIT) Bombay in 2010 and specialized in VLSI Design & Nanotechnology during my 3-year tenure at IIT Bombay, from 2007 - 2010.

Corporate Life @

1) Lead Physical design and STA engineer, Qualcomm, Bangalore India, 07/2010-04/2013

2) Lead Sales Application engineer, Cadence Design systems, Bangalore India, 04/2013-01/17

Hands on with Technology @

1) MSM (mobile station mode chips) - MSM chips are used for CDMA modulation/demodulation. It consists of DSP’s and microprocessors for running applications such as web-browsing, video conferencing, multimedia services, etc.

2) Memory test chips - Memory test chips are used to validate functionality of 28nm custom/compiler memory as well as characterize their timing, power and yield.

3) DDR-PHY test chips - DDR-PHY test chips are basically tested for high speed data transfer

4) Timing and physical design Flow development for 130nm MOSFET technology node till 16nm FinFET technology node.

5) “IR aware STAandLow power STA

6) Analyzed STA engine behavior for design size up to 850 million instance count

ACADEMIC

1) Research Assistant to Prof. Richard Pinto and Prof. Anil Kottantharayil on “Sub-100nm optimization using Electron Beam Lithography”, which intended to optimize RAITH-150TWO Electron Beam Lithography tool and the process conditions to attain minimum resolution, use the mix-and-match capabilities of the tool for sub-100nm MOSFET fabrication and generate mask plates for feature sizes above 500nm.

2) Research Assistant to with Prof. Madhav Desai, to characterize RTL, generated from C-to-RTL AHIR compiler, in terms of power, performance and area. This was done by passing RTL, generated from AHIR compiler, through standard ASIC tool chain like synthesis and place & route. The resulting netlist out of PNR was characterized using standard software

PUBLICATION 

1) “A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems” submitted in the conference “13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France

2) Concurrent + Distributed MMMC STA for 'N' views

3) Signoff Timing and Leakage Optimization On 18M Instance Count Design With 8000 Clocks and Replicated Modules Using Master Clone Methodology With EDI Cockpit

4) Placement-aware ECO Methodology - No Slacking on Slack

Online Presence - Courses on Udemy

Now, to be really successful in the field of VLSI and Semiconductors, you need to take the courses in below order:

1) VSD - Physical design flow

2) VSD - Clock tree synthesis - Part 1 & 2

3) VSD - Signal Integrity

4) VSD - Static timing analysis - Part 1 & 2 (Can be taken in between)

5) VSD - Circuit design and SPICE simulations Part 1 & Part 2 (This is the core of VLSI, so you can take it in beginning or end)

6) VLSI - Essential concepts and detailed interview guide (This course is a glimpse of all above courses, but for details of each topic, you need to take course 1) to 5).)

7) VSD - Custom Layout (Can be taken in between) 

8) VSD - Library characterization and modelling - Part 1 (STA-1 and 2, Circuit design and SPICE simulations-1 and 2 are mandatory)

Connect with me for more guidance !!

Hope you enjoy the session best of luck for future !!