VLSI - Essential concepts and detailed interview guide

VLSI Academy
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  • Lectures 72
  • Length 11.5 hours
  • Skill Level All Levels
  • Languages English
  • Includes Lifetime access
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About This Course

Published 6/2013 English

Course Description

This course is about Basic concepts of VLSI System Design. The course is designed in the form of micro-videos, which delivers content in the form of Info-Graphics. It is designed for self-learning and will help to polish the Industrial skills in VLSI World. This course will cover end-to-end description from basic Device Physics to Chip Design.The introductory video series focuses on the basic elemental physics and electrical characteristics of MOS Transistor.
Do visit our website: www.vlsisystemdesign.com...
Learn Advance VLSI Concepts in Our New Video Series
@ https://www.udemy.com/vlsi-academy-clock-tree-synthesis/

What are the requirements?

  • Individuals having Basic Knowledge of Electrical and Electronics

What am I going to get from this course?

  • To bridge the gap between Understanding and Application of Knowledge, this leads to innovation

What is the target audience?

  • Individuals keen to learn about VLSI and Chip World

What you get with this course?

Not for you? No problem.
30 day money back guarantee.

Forever yours.
Lifetime access.

Learn on the go.
Desktop, iOS and Android.

Get rewarded.
Certificate of completion.

Curriculum

Section 1: Physical Design Flow Overview
Floor-Planning Steps
Preview
10:36
Netlist Binding And Placement Optimization
09:34
Clock Net Shielding
09:34
Route - DRC Clean - Parasitics Extraction - Final STA
09:33
Section 2: Floorplanning
Utilization Factor And Aspect Ratio
09:10
Concept of Pre-placed Cells
09:27
Power Planning
10:26
Pin Placement And Logical Cell Placement Blockage
09:34
Section 3: Placement
Netlist Binding And Placement
09:22
Optimize Placement Using Estimated Wire Length And Capacitance
10:02
Optimize Placement Continued
08:48
Section 4: Timing Analysis With Ideal Clocks
Setup Time Analysis And Introduction To Flip-Flop Setup Time
09:44
Setup Timing Analysis With Multiple Clocks
08:49
Multiple Clock Timing Analysis And Introduction To Data Slew Check
09:06
Data Slew Check
09:21
Section 5: Clock Tree Synthesis - Introduction And Quality Check Parameters
Introduction To Clock Tree Synthesis
10:05
Duty Cycle And Latency Check
10:15
Latency And Power Check
10:20
Power And Crosstalk Quality Check
10:46
Glitch Quality Check
07:34
Section 6: H-Tree
H-Tree Algorithm And Skew Check
09:41
H-Tree Pulse Width And Duty Cycle Check
09:51
H-Tree Latency And Power Check
09:58
Section 7: Clock Tree Modelling and Observations
Clock Tree Modelling
09:26
Clock Tree Building
09:58
Clock Tree Observations
09:27
Section 8: Buffered H-Tree
H-Tree Buffering Observations
11:06
H-Tree Pulse Width Check And Issues With Regular Buffers
09:13
CMOS Inverter PMOS/NMOS Matching Switching Resistance Solution
09:51
H-Tree Clock Buffers And Pulse Width Check
10:48
Dynamic Power And Short Circuit Power
09:46
Section 9: Clock Tree Optimization Checklist
Optimization Checklist
09:48
Leakage Current Reduction Technique
09:35
Optimized Clock Tree Power And Latency Check
06:44
Section 10: Static Timing Analysis With Real Clocks
Static Timing Analysis With Real Clocks
09:48
Impact Of Unbalanced Skew On Setup Time
10:00
Impact Of Unbalanced Skew On Hold Time
11:19
Section 11: Introduction To Crosstalk - Why and How Crosstalk occurs in a CHIP ??
Introduction
08:16
Dominant Lateral Capacitance
09:29
Noise Margin Voltage Parameters
08:56
Lower Supply Voltage
10:12
Section 12: Glitch Examples And Factors Affecting Glitch Height
Basic Crosstalk Glitch Example
09:58
Glitch Discharge With High Drive Strength PMOS Transistor
10:16
Factors Affecting Glitch Height - Aggressor Drive Strength
10:28
Factors Affecting Glitch Height - Conclusion
10:13
Section 13: Tolerable Glitch Heights and Introduction to AC Noise Margin
Impacts Of Glitch
10:20
Tolerable Glitch Heights Using DC Noise Margin
09:12
AC Noise Margin
08:29
Justification Of Load Impact And Conclusion
09:00
Section 14: Crosstalk Delta Delay Analysis
Crosstalk Delta Delay - Aggressor Victim Switching in Opposite Direction
09:16
Setup Timing Analysis Using Real Clocks
10:13
Crosstalk Delta Delay - Aggressor Victim Switching In Same Direction
08:39
Impact Of Crosstalk Delta Delay On Hold Timing
08:27
Section 15: Noise Protection Technique
Shielding
08:34
Spacing
09:04
Drive Strength
11:07
Section 16: Routing And Design Rule Check (DRC)
Introduction To Maze Routing - Lee's Algorithm
08:42
Design Rule Check
09:53
Section 17: Parasitics Extraction
Introduction To IEEE 1481-1999 SPEF Format
09:20
SPEF Header Description, Physical Design Flow Conclusion And What Next !!
08:22
Section 18: GENERATED CLOCKS DEFINITION AND CREATION
DEFINE GENERATED CLOCK FOR DIVIDE-BY-2 CIRCUIT
08:59
GENERATED CLOCKS USING MASTER CLOCK EDGES
09:45
GENERATED CLOCK WAVEFORM DERIVATION
08:21
GENERATED CLOCK WITH SHIFTED EDGE
07:23
Section 19: BASICS OF MOS TRANSISTOR
09:01

This video briefly explains structure of NMOS

For more Information visit www.vlsisystemdesign.com

10:10

This video briefly explains structure of NMOS.
For more Information visit : www.vlsisystemdesign.com

09:01

This video briefly explains structure of NMOS.
For more Information visit : www.vlsisystemdesign.com

IMPACT OF SUBSTRATE POTENTIAL ON THRESHOLD VOLTAGE (VT)
09:57
Section 20: SETUP & HOLD TIMING ANALYSIS
INITIAL TIMING ANALYSIS AND INTRODUCTION TO FLOP SETUP TIME
10:09
SETUP TIMING ANALYSIS WITH JITTER AND REAL CLOCKS
08:32
INTRODUCTION TO SLACK AND HOLD TIMING ANALYSIS
09:51
HOLD TIMING ANALYSIS CONCLUDED
04:53

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Instructor Biography

Kunal Ghosh, Educator & VLSI Expertise from IIT Bombay India

Kunal Ghosh, an Engineer by qualification and Educator by interest. It gives me great energy to help students to understand the Concepts of VLSI and Chip Design used in semiconductor Industry and assist them to achieve goals in Professional world. My course are product of simple Principle I follow at work, Keep it Simple and Sweet, All my lectures are full of info-graphical video, where pictures speaks louder then my words.

Now, to be really successful in the field of VLSI and Semiconductors, you need to take the courses in below order:

1) VLSI Academy - Physical design flow

2) VLSI Academy - Clock tree synthesis - Part 1 & 2

3) VLSI Academy - Signal Integrity

4) VLSI Academy - Static timing analysis (Can be taken in between)

5) VLSI Academy - Circuit design and SPICE simulations Part 1 & Part 2 (This is the core of VLSI, so you can take it in beginning or end)

6) VLSI - Essential concepts and detailed interview guide (This course is a glimpse of all above courses, but for details of each topic, you need to take course 1) to 5).)

Connect with me for more guidance !!

Hope you enjoy the session best of luck for future !!

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