VLSI - Essential concepts and detailed interview guide
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This course is about Basic concepts of VLSI System Design. The course is designed in the form of micro-videos, which delivers content in the form of Info-Graphics. It is designed for self-learning and will help to polish the Industrial skills in VLSI World. This course will cover end-to-end description from basic Device Physics to Chip Design.The introductory video series focuses on the basic elemental physics and electrical characteristics of MOS Transistor.
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|Section 1: Physical Design Flow Overview|
Netlist Binding And Placement Optimization
Clock Net Shielding
Route - DRC Clean - Parasitics Extraction - Final STA
|Section 2: Floorplanning|
Utilization Factor And Aspect Ratio
Concept of Pre-placed Cells
Pin Placement And Logical Cell Placement Blockage
|Section 3: Placement|
Netlist Binding And Placement
Optimize Placement Using Estimated Wire Length And Capacitance
Optimize Placement Continued
|Section 4: Timing Analysis With Ideal Clocks|
Setup Time Analysis And Introduction To Flip-Flop Setup Time
Setup Timing Analysis With Multiple Clocks
Multiple Clock Timing Analysis And Introduction To Data Slew Check
Data Slew Check
|Section 5: Clock Tree Synthesis - Introduction And Quality Check Parameters|
Introduction To Clock Tree Synthesis
Duty Cycle And Latency Check
Latency And Power Check
Power And Crosstalk Quality Check
Glitch Quality Check
|Section 6: H-Tree|
H-Tree Algorithm And Skew Check
H-Tree Pulse Width And Duty Cycle Check
H-Tree Latency And Power Check
|Section 7: Clock Tree Modelling and Observations|
Clock Tree Modelling
Clock Tree Building
Clock Tree Observations
|Section 8: Buffered H-Tree|
H-Tree Buffering Observations
H-Tree Pulse Width Check And Issues With Regular Buffers
CMOS Inverter PMOS/NMOS Matching Switching Resistance Solution
H-Tree Clock Buffers And Pulse Width Check
Dynamic Power And Short Circuit Power
|Section 9: Clock Tree Optimization Checklist|
Leakage Current Reduction Technique
Optimized Clock Tree Power And Latency Check
|Section 10: Static Timing Analysis With Real Clocks|
Static Timing Analysis With Real Clocks
Impact Of Unbalanced Skew On Setup Time
Impact Of Unbalanced Skew On Hold Time
|Section 11: Introduction To Crosstalk - Why and How Crosstalk occurs in a CHIP ??|
Dominant Lateral Capacitance
Noise Margin Voltage Parameters
Lower Supply Voltage
|Section 12: Glitch Examples And Factors Affecting Glitch Height|
Basic Crosstalk Glitch Example
Glitch Discharge With High Drive Strength PMOS Transistor
Factors Affecting Glitch Height - Aggressor Drive Strength
Factors Affecting Glitch Height - Conclusion
|Section 13: Tolerable Glitch Heights and Introduction to AC Noise Margin|
Impacts Of Glitch
Tolerable Glitch Heights Using DC Noise Margin
AC Noise Margin
Justification Of Load Impact And Conclusion
|Section 14: Crosstalk Delta Delay Analysis|
Crosstalk Delta Delay - Aggressor Victim Switching in Opposite Direction
Setup Timing Analysis Using Real Clocks
Crosstalk Delta Delay - Aggressor Victim Switching In Same Direction
Impact Of Crosstalk Delta Delay On Hold Timing
|Section 15: Noise Protection Technique|
|Section 16: Routing And Design Rule Check (DRC)|
Introduction To Maze Routing - Lee's Algorithm
Design Rule Check
|Section 17: Parasitics Extraction|
Introduction To IEEE 1481-1999 SPEF Format
SPEF Header Description, Physical Design Flow Conclusion And What Next !!
|Section 18: GENERATED CLOCKS DEFINITION AND CREATION|
DEFINE GENERATED CLOCK FOR DIVIDE-BY-2 CIRCUIT
GENERATED CLOCKS USING MASTER CLOCK EDGES
GENERATED CLOCK WAVEFORM DERIVATION
GENERATED CLOCK WITH SHIFTED EDGE
|Section 19: BASICS OF MOS TRANSISTOR|
This video briefly explains structure of NMOS
For more Information visit www.vlsisystemdesign.com
This video briefly explains structure of NMOS.
This video briefly explains structure of NMOS.
IMPACT OF SUBSTRATE POTENTIAL ON THRESHOLD VOLTAGE (VT)
|Section 20: SETUP & HOLD TIMING ANALYSIS|
INITIAL TIMING ANALYSIS AND INTRODUCTION TO FLOP SETUP TIME
SETUP TIMING ANALYSIS WITH JITTER AND REAL CLOCKS
INTRODUCTION TO SLACK AND HOLD TIMING ANALYSIS
HOLD TIMING ANALYSIS CONCLUDED
Kunal Ghosh, an Engineer by qualification and Educator by interest. It gives me great energy to help students to understand the Concepts of VLSI and Chip Design used in semiconductor Industry and assist them to achieve goals in Professional world. My course are product of simple Principle I follow at work, Keep it Simple and Sweet, All my lectures are full of info-graphical video, where pictures speaks louder then my words.
Now, to be really successful in the field of VLSI and Semiconductors, you need to take the courses in below order:
1) VLSI Academy - Physical design flow
2) VLSI Academy - Clock tree synthesis - Part 1 & 2
3) VLSI Academy - Signal Integrity
4) VLSI Academy - Static timing analysis (Can be taken in between)
5) VLSI Academy - Circuit design and SPICE simulations Part 1 & Part 2 (This is the core of VLSI, so you can take it in beginning or end)
6) VLSI - Essential concepts and detailed interview guide (This course is a glimpse of all above courses, but for details of each topic, you need to take course 1) to 5).)
Connect with me for more guidance !!
Hope you enjoy the session best of luck for future !!