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VSD - Static Timing Analysis - I

VLSI - Essential timing checks
Bestselling
4.3 (153 ratings)
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602 students enrolled
Created by Kunal Ghosh
Last updated 4/2016
English
$15 $95 84% off
30-Day Money-Back Guarantee
Includes:
  • 3.5 hours on-demand video
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
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Description

Static timing analysis comprises broadly for timing checks, constraints and library. Having all of them in a single course makes it bulky. So we decided to have it in 3 parts and this is part I - Essential timing checks. This course will give an eagle's eye to every timing check that is being performed in current industries for sign-off. This will also introduce you to basic terminologies for timing, which are needed for advanced courses on STA.

Timing comes at every step of physical design flow, but in this course, we primarily focus on signoff timing i.e. looking into each and every corner of design for any timing violations

The course starts from very basic and gradually takes you to an advanced level at an intermediate pace. So no questions on you missing any details

Hope you enjoy learning this course in the same way we enjoyed making them.

Happy Learning !!

Who is the target audience?
  • Course starts from basic timing path to advanced latch checks, so basics of flipflops should be enough
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What Will I Learn?
Understand various STA checks for timing closure
Able to do a quality analysis for real designs
Know-how on how real STA works in industries, something which you will not find in any books
Step-by-step and structured timing analysis
View Curriculum
Requirements
  • Knowledge on physical design flow will be good to have
  • If not, no worries. This course will take you from basics to advanced in a structured manner and create an interest in physical design world
Curriculum For This Course
Expand All 28 Lectures Collapse All 28 Lectures 03:28:43
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Introduction and agenda
6 Lectures 40:58

Introduction to timing path and arrival time
08:04

Introduction to required time and slack
07:32

Introduction to basic categories of setup and hold analysis
08:05


Introduction to slew, load and clock checks
06:52
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First things first - Introduction to timing graph
5 Lectures 40:24
Convert logic gates into nodes
08:22

Compute actual arrival time (AAT)
08:24

Compute required arrival time (RAT)
07:00

Compute slack and introduction to GBA-PBA analysis
08:12

Convert pins to nodes and compute AAT, RAT and slack
08:26
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Clk-to-q delay, library setup, hold time and jitter
6 Lectures 42:47
Introduction to transistor level circuit for flops
06:46

Negative and positive latch transistor level operation
06:39

Library setup time calculation
07:25

Clk-q delay calculation
08:06

Steps to create eye diagram for jitter analysis
06:58

Jitter extraction and accounting in setup timing analysis
06:53
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Textual timing reports and hold analysis
3 Lectures 21:57
Setup analysis - graphical to textual representation
07:08

Hold analysis with real clocks
08:24

Hold analysis - graphical to textual representation
06:25
+
On-chip variation
3 Lectures 28:07
Sources of variation - etching
09:40

Sources of variation - oxide thickness
07:50

Relationship between resistance, drain current and delay
10:37
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OCV timing and pessimism removal
4 Lectures 32:30
OCV based setup timing analysis
09:17

Setup timing analysis after pessimism removal
08:49

OCV based hold timing analysis
05:34

Hold timing analysis after pessimism removal
08:50
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Conclusion
1 Lecture 02:00
About the Instructor
4.4 Average rating
1,017 Reviews
10,681 Students
11 Courses
Growth Hacker & Co-Founder at VLSI System Design(VSD)

As a 'Growth Hacker', I intend to help students/professionals build their profile even stronger in semiconductors and VLSI, by creating courses at every possible domain in Back end. The experiments which I perform in VSD courses using open-source EDA tools, are of similar complexity of current chip design industry. Till date I have nurtured around 10000+ students and professionals through videos and many of them have been placed or moved to leading semiconductor industries. I have been doing this part time for past 6 years, and now doing this full time at VSD. Happy Learning!!

Now, to be really successful in the field of VLSI and Semiconductors, you need to take the courses in below order:

1) VSD - Physical design flow

2) VSD - Clock tree synthesis - Part 1 & 2

3) VSD - Signal Integrity

4) VSD - Static timing analysis - Part 1 & 2 (Can be taken in between)

5) VSD - Circuit design and SPICE simulations Part 1 & Part 2 (This is the core of VLSI, so you can take it in beginning or end)

6) VLSI - Essential concepts and detailed interview guide (This course is a glimpse of all above courses, but for details of each topic, you need to take course 1) to 5).)

7) VSD - Custom Layout (Can be taken in between)

Connect with me for more guidance !!

Hope you enjoy the session best of luck for future !!

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