VSD - Static Timing Analysis - I
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VSD - Static Timing Analysis - I

VLSI - Essential timing checks
Best Seller
4.4 (317 ratings)
Instead of using a simple lifetime average, Udemy calculates a course's star rating by considering a number of different factors such as the number of ratings, the age of ratings, and the likelihood of fraudulent ratings.
1,069 students enrolled
Created by Kunal Ghosh
Last updated 4/2016
English
Current price: $12 Original price: $95 Discount: 87% off
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Includes:
  • 3.5 hours on-demand video
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion

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What Will I Learn?
  • Understand various STA checks for timing closure
  • Able to do a quality analysis for real designs
  • Know-how on how real STA works in industries, something which you will not find in any books
  • Step-by-step and structured timing analysis
View Curriculum
Requirements
  • Knowledge on physical design flow will be good to have
  • If not, no worries. This course will take you from basics to advanced in a structured manner and create an interest in physical design world
Description

Static timing analysis comprises broadly for timing checks, constraints and library. Having all of them in a single course makes it bulky. So we decided to have it in 3 parts and this is part I - Essential timing checks. This course will give an eagle's eye to every timing check that is being performed in current industries for sign-off. This will also introduce you to basic terminologies for timing, which are needed for advanced courses on STA.

Timing comes at every step of physical design flow, but in this course, we primarily focus on signoff timing i.e. looking into each and every corner of design for any timing violations

The course starts from very basic and gradually takes you to an advanced level at an intermediate pace. So no questions on you missing any details

Hope you enjoy learning this course in the same way we enjoyed making them.

Happy Learning !!

Who is the target audience?
  • Course starts from basic timing path to advanced latch checks, so basics of flipflops should be enough
Compare to Other Static Timing Analysis Courses
Curriculum For This Course
28 Lectures
03:28:43
+
Introduction and agenda
6 Lectures 40:58

Introduction to timing path and arrival time
08:04

Introduction to required time and slack
07:32

Introduction to basic categories of setup and hold analysis
08:05


Introduction to slew, load and clock checks
06:52
+
First things first - Introduction to timing graph
5 Lectures 40:24
Convert logic gates into nodes
08:22

Compute actual arrival time (AAT)
08:24

Compute required arrival time (RAT)
07:00

Compute slack and introduction to GBA-PBA analysis
08:12

Convert pins to nodes and compute AAT, RAT and slack
08:26
+
Clk-to-q delay, library setup, hold time and jitter
6 Lectures 42:47
Introduction to transistor level circuit for flops
06:46

Negative and positive latch transistor level operation
06:39

Library setup time calculation
07:25

Clk-q delay calculation
08:06

Steps to create eye diagram for jitter analysis
06:58

Jitter extraction and accounting in setup timing analysis
06:53
+
Textual timing reports and hold analysis
3 Lectures 21:57
Setup analysis - graphical to textual representation
07:08

Hold analysis with real clocks
08:24

Hold analysis - graphical to textual representation
06:25
+
On-chip variation
3 Lectures 28:07
Sources of variation - etching
09:40

Sources of variation - oxide thickness
07:50

Relationship between resistance, drain current and delay
10:37
+
OCV timing and pessimism removal
4 Lectures 32:30
OCV based setup timing analysis
09:17

Setup timing analysis after pessimism removal
08:49

OCV based hold timing analysis
05:34

Hold timing analysis after pessimism removal
08:50
+
Conclusion
1 Lecture 02:00
About the Instructor
Kunal Ghosh
4.4 Average rating
1,912 Reviews
13,298 Students
15 Courses
Digital and Sign-off expert at VLSI System Design(VSD)

I received MTech Degree in Department of Electrical Engineering (EE) from Indian Institute of Technology (IIT) Bombay in 2010 and specialized in VLSI Design & Nanotechnology during my 3-year tenure at IIT Bombay, from 2007 - 2010.

Corporate Life @

1) Lead Physical design and STA engineer, Qualcomm, Bangalore India, 07/2010-04/2013

2) Lead Sales Application engineer, Cadence Design systems, Bangalore India, 04/2013-01/17

Hands on with Technology @

1) MSM (mobile station mode chips) - MSM chips are used for CDMA modulation/demodulation. It consists of DSP’s and microprocessors for running applications such as web-browsing, video conferencing, multimedia services, etc.

2) Memory test chips - Memory test chips are used to validate functionality of 28nm custom/compiler memory as well as characterize their timing, power and yield.

3) DDR-PHY test chips - DDR-PHY test chips are basically tested for high speed data transfer

4) Timing and physical design Flow development for 130nm MOSFET technology node till 16nm FinFET technology node.

5) “IR aware STAandLow power STA

6) Analyzed STA engine behavior for design size up to 850 million instance count

ACADEMIC

1) Research Assistant to Prof. Richard Pinto and Prof. Anil Kottantharayil on “Sub-100nm optimization using Electron Beam Lithography”, which intended to optimize RAITH-150TWO Electron Beam Lithography tool and the process conditions to attain minimum resolution, use the mix-and-match capabilities of the tool for sub-100nm MOSFET fabrication and generate mask plates for feature sizes above 500nm.

2) Research Assistant to with Prof. Madhav Desai, to characterize RTL, generated from C-to-RTL AHIR compiler, in terms of power, performance and area. This was done by passing RTL, generated from AHIR compiler, through standard ASIC tool chain like synthesis and place & route. The resulting netlist out of PNR was characterized using standard software

PUBLICATION 

1) “A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems” submitted in the conference “13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France

2) Concurrent + Distributed MMMC STA for 'N' views

3) Signoff Timing and Leakage Optimization On 18M Instance Count Design With 8000 Clocks and Replicated Modules Using Master Clone Methodology With EDI Cockpit

4) Placement-aware ECO Methodology - No Slacking on Slack

Online Presence - Courses on Udemy

Now, to be really successful in the field of VLSI and Semiconductors, you need to take the courses in below order:

1) VSD - Physical design flow

2) VSD - Clock tree synthesis - Part 1 & 2

3) VSD - Signal Integrity

4) VSD - Static timing analysis - Part 1 & 2 (Can be taken in between)

5) VSD - Circuit design and SPICE simulations Part 1 & Part 2 (This is the core of VLSI, so you can take it in beginning or end)

6) VLSI - Essential concepts and detailed interview guide (This course is a glimpse of all above courses, but for details of each topic, you need to take course 1) to 5).)

7) VSD - Custom Layout (Can be taken in between) 

8) VSD - Library characterization and modelling - Part 1 (STA-1 and 2, Circuit design and SPICE simulations-1 and 2 are mandatory)

Connect with me for more guidance !!

Hope you enjoy the session best of luck for future !!