VSD - Static Timing Analysis - I

Essential timing checks
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554 students enrolled Bestselling in VLSI
Instructed by Kunal Ghosh Design / Design Tools
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  • Lectures 28
  • Length 3.5 hours
  • Skill Level All Levels
  • Languages English
  • Includes Lifetime access
    30 day money back guarantee!
    Available on iOS and Android
    Certificate of Completion
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About This Course

Published 2/2016 English

Course Description

Static timing analysis comprises broadly for timing checks, constraints and library. Having all of them in a single course makes it bulky. So we decided to have it in 3 parts and this is part I - Essential timing checks. This course will give an eagle's eye to every timing check that is being performed in current industries for sign-off. This will also introduce you to basic terminologies for timing, which are needed for advanced courses on STA.

Timing comes at every step of physical design flow, but in this course, we primarily focus on signoff timing i.e. looking into each and every corner of design for any timing violations

The course starts from very basic and gradually takes you to an advanced level at an intermediate pace. So no questions on you missing any details

Hope you enjoy learning this course in the same way we enjoyed making them.

Happy Learning !!

What are the requirements?

  • Knowledge on physical design flow will be good to have
  • If not, no worries. This course will take you from basics to advanced in a structured manner and create an interest in physical design world

What am I going to get from this course?

  • Understand various STA checks for timing closure
  • Able to do a quality analysis for real designs
  • Know-how on how real STA works in industries, something which you will not find in any books
  • Step-by-step and structured timing analysis

Who is the target audience?

  • Course starts from basic timing path to advanced latch checks, so basics of flipflops should be enough

What you get with this course?

Not for you? No problem.
30 day money back guarantee.

Forever yours.
Lifetime access.

Learn on the go.
Desktop, iOS and Android.

Get rewarded.
Certificate of completion.


Section 1: Introduction and agenda
Introduction to timing path and arrival time
Introduction to required time and slack
Introduction to basic categories of setup and hold analysis
Introduction to data check and latch timing
Introduction to slew, load and clock checks
Section 2: First things first - Introduction to timing graph
Convert logic gates into nodes
Compute actual arrival time (AAT)
Compute required arrival time (RAT)
Compute slack and introduction to GBA-PBA analysis
Convert pins to nodes and compute AAT, RAT and slack
Section 3: Clk-to-q delay, library setup, hold time and jitter
Introduction to transistor level circuit for flops
Negative and positive latch transistor level operation
Library setup time calculation
Clk-q delay calculation
Steps to create eye diagram for jitter analysis
Jitter extraction and accounting in setup timing analysis
Section 4: Textual timing reports and hold analysis
Setup analysis - graphical to textual representation
Hold analysis with real clocks
Hold analysis - graphical to textual representation
Section 5: On-chip variation
Sources of variation - etching
Sources of variation - oxide thickness
Relationship between resistance, drain current and delay
Section 6: OCV timing and pessimism removal
OCV based setup timing analysis
Setup timing analysis after pessimism removal
OCV based hold timing analysis
Hold timing analysis after pessimism removal
Section 7: Conclusion
Conclusion and next topics!!

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Instructor Biography

Kunal Ghosh, Growth Hacker & Co-Founder at VLSI System Design(VSD)

As a 'Growth Hacker', I intend to help students/professionals build their profile even stronger in semiconductors and VLSI, by creating courses at every possible domain in Back end. The experiments which I perform in VSD courses using open-source EDA tools, are of similar complexity of current chip design industry. Till date I have nurtured around 10000+ students and professionals through videos and many of them have been placed or moved to leading semiconductor industries. I have been doing this part time for past 6 years, and now doing this full time at VSD. Happy Learning!!

Now, to be really successful in the field of VLSI and Semiconductors, you need to take the courses in below order:

1) VSD - Physical design flow

2) VSD - Clock tree synthesis - Part 1 & 2

3) VSD - Signal Integrity

4) VSD - Static timing analysis - Part 1 & 2 (Can be taken in between)

5) VSD - Circuit design and SPICE simulations Part 1 & Part 2 (This is the core of VLSI, so you can take it in beginning or end)

6) VLSI - Essential concepts and detailed interview guide (This course is a glimpse of all above courses, but for details of each topic, you need to take course 1) to 5).)

7) VSD - Custom Layout (Can be taken in between)

Connect with me for more guidance !!

Hope you enjoy the session best of luck for future !!

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