VLSI Academy - Static Timing Analysis - I

Essential timing checks
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464 students enrolled Bestselling in VLSI
Instructed by Kunal Ghosh Design / Design Tools
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  • Lectures 28
  • Length 3.5 hours
  • Skill Level All Levels
  • Languages English
  • Includes Lifetime access
    30 day money back guarantee!
    Available on iOS and Android
    Certificate of Completion
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About This Course

Published 2/2016 English

Course Description

Static timing analysis comprises broadly for timing checks, constraints and library. Having all of them in a single course makes it bulky. So we decided to have it in 3 parts and this is part I - Essential timing checks. This course will give an eagle's eye to every timing check that is being performed in current industries for sign-off. This will also introduce you to basic terminologies for timing, which are needed for advanced courses on STA.

Timing comes at every step of physical design flow, but in this course, we primarily focus on signoff timing i.e. looking into each and every corner of design for any timing violations

The course starts from very basic and gradually takes you to an advanced level at an intermediate pace. So no questions on you missing any details

Hope you enjoy learning this course in the same way we enjoyed making them.

Happy Learning !!

What are the requirements?

  • Knowledge on physical design flow will be good to have
  • If not, no worries. This course will take you from basics to advanced in a structured manner and create an interest in physical design world

What am I going to get from this course?

  • Understand various STA checks for timing closure
  • Able to do a quality analysis for real designs
  • Know-how on how real STA works in industries, something which you will not find in any books
  • Step-by-step and structured timing analysis

What is the target audience?

  • Course starts from basic timing path to advanced latch checks, so basics of flipflops should be enough

What you get with this course?

Not for you? No problem.
30 day money back guarantee.

Forever yours.
Lifetime access.

Learn on the go.
Desktop, iOS and Android.

Get rewarded.
Certificate of completion.

Curriculum

Section 1: Introduction and agenda
Introduction
Preview
02:35
Introduction to timing path and arrival time
08:04
Introduction to required time and slack
07:32
Introduction to basic categories of setup and hold analysis
08:05
Introduction to data check and latch timing
Preview
07:50
Introduction to slew, load and clock checks
06:52
Section 2: First things first - Introduction to timing graph
Convert logic gates into nodes
08:22
Compute actual arrival time (AAT)
08:24
Compute required arrival time (RAT)
07:00
Compute slack and introduction to GBA-PBA analysis
08:12
Convert pins to nodes and compute AAT, RAT and slack
08:26
Section 3: Clk-to-q delay, library setup, hold time and jitter
Introduction to transistor level circuit for flops
06:46
Negative and positive latch transistor level operation
06:39
Library setup time calculation
07:25
Clk-q delay calculation
08:06
Steps to create eye diagram for jitter analysis
06:58
Jitter extraction and accounting in setup timing analysis
06:53
Section 4: Textual timing reports and hold analysis
Setup analysis - graphical to textual representation
07:08
Hold analysis with real clocks
08:24
Hold analysis - graphical to textual representation
06:25
Section 5: On-chip variation
Sources of variation - etching
09:40
Sources of variation - oxide thickness
07:50
Relationship between resistance, drain current and delay
10:37
Section 6: OCV timing and pessimism removal
OCV based setup timing analysis
09:17
Setup timing analysis after pessimism removal
08:49
OCV based hold timing analysis
05:34
Hold timing analysis after pessimism removal
08:50
Section 7: Conclusion
Conclusion and next topics!!
Preview
02:00

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Instructor Biography

Kunal Ghosh, Educator & VLSI Expertise from IIT Bombay India

Kunal Ghosh, an Engineer by qualification and Educator by interest. It gives me great energy to help students to understand the Concepts of VLSI and Chip Design used in semiconductor Industry and assist them to achieve goals in Professional world. My course are product of simple Principle I follow at work, Keep it Simple and Sweet, All my lectures are full of info-graphical video, where pictures speaks louder then my words.

Now, to be really successful in the field of VLSI and Semiconductors, you need to take the courses in below order:

1) VLSI Academy - Physical design flow

2) VLSI Academy - Clock tree synthesis - Part 1 & 2

3) VLSI Academy - Signal Integrity

4) VLSI Academy - Static timing analysis (Can be taken in between)

5) VLSI Academy - Circuit design and SPICE simulations Part 1 & Part 2 (This is the core of VLSI, so you can take it in beginning or end)

6) VLSI - Essential concepts and detailed interview guide (This course is a glimpse of all above courses, but for details of each topic, you need to take course 1) to 5).)

Connect with me for more guidance !!

Hope you enjoy the session best of luck for future !!

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