VSD - Static Timing Analysis - II
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VSD - Static Timing Analysis - II

VLSI - Analyse your chip timing for free
4.6 (58 ratings)
Instead of using a simple lifetime average, Udemy calculates a course's star rating by considering a number of different factors such as the number of ratings, the age of ratings, and the likelihood of fraudulent ratings.
592 students enrolled
Created by Kunal Ghosh
Last updated 7/2017
Current price: $10 Original price: $95 Discount: 89% off
5 hours left at this price!
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  • 4 hours on-demand video
  • 7 Articles
  • 2 Supplemental Resources
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
What Will I Learn?
  • Students will be able to do a real full chip static timing analysis with $0 spent, as designs and tools used in this course are opensource
  • Students will be able to appreciate power of opensource EDA tools, like Opentimer used in this course, and help in contributing towards the development of this tool
View Curriculum
  • Static Timing analysis - part 1 course needs to be fully completed to start this course. No exceptions
  • Knowledge of physical design flow and clock tree synthesis will be helpful

In static timing analysis - part 1 course, we introduced you to basic and essential timing checks, like cppr, gba, pba, etc. In this course, we are focusing on application of these concepts on real chip using opensource sta tool called 'Opentimer'. There is an amount of homework needed to make this tool work, but you know what, looking and feeling the power of this opensource tool, you will find the effort is worth taking

Why its worth? Because, you can now analyze your chip at $0 right from your home. Isn't that FREEdom that we have been looking for? In my advanced courses, including this one, the prime focus is on how to analyze complex chips like USB controller or DDR using Opentimer.

Opentimer has been developed by Tsung-Wei Huang and Prof. Martin D. F. Wong in the University of Illinios at Urbana-Champaign (UIUC), IL, USA. It supports important features like PBA, CPPR, block based analysis, and many more. 

I am using this tool in this course for explaining the concepts from STA-part 1 and also for some interface analysis that we will be looking in this course.

So, hope you enjoy learning this course in the same way we enjoyed making them.

Happy Learning !!

Who is the target audience?
  • Anyone who has completed static timing analysis - part 1 course
  • Anyone (with 100% static timing analysis - part 1 course completed) who has basic knowledge on flipflops, gates and digital logic
Compare to Other Static Timing Analysis Courses
Curriculum For This Course
37 Lectures
Introduction to sta-2 and opentimer tool
2 Lectures 11:52

Introduction to opentimer, netlist definition and my_run.tcl creation
Constraints creation commands for Opentimer
5 Lectures 30:26
Clock creation and clock arrival time definitions

Clock slew and data slew constraints

Output load and output delay constraints

my_run.tcl for above experiments
Full reg2reg analysis using OpenTimer tool
7 Lectures 22:39
Actual arrival time (AAT) and required arrival time (RAT) calculation basics

Slack compute, pesimissim (cppr) and engineering change order (eco)

Interface analysis
9 Lectures 01:05:11
Introduction to interface analysis

Case1 : C2Q and combinational delay for input is known

Case2 : Input waveform specifications given

Case 3 : setup_time, hold_time and combinational delay for output is known

Case 5 : Source synchronous interface analysis for setup

Source synchronous interface setup analysis in Opentimer tool

Source synchronous interface hold analysis
Clock gating analysis
5 Lectures 39:53
Introduction to clock gating analysis

Active high clock gating analysis

Active low clock gating analysis

Integrated clock gating (ICG) cell
Asynchronous and data checks
4 Lectures 33:16
Inception of asynchronous reset design technique

Data-to-data setup and hold check

Sequential and clock tree min pulse width check
Latch timing and load/slew analysis
4 Lectures 36:46
Introduction to positive and negative latch behavior

Reg2Latch path with 'time borrow' and 'time given' examples

Introduction to different kinds of power

(Snippet for CTS course) Load and slew inter-dependence
1 Lecture 01:55
Conclusion, acknowledgements and what next!!!
About the Instructor
Kunal Ghosh
4.4 Average rating
1,895 Reviews
13,256 Students
15 Courses
Digital and Sign-off expert at VLSI System Design(VSD)

I received MTech Degree in Department of Electrical Engineering (EE) from Indian Institute of Technology (IIT) Bombay in 2010 and specialized in VLSI Design & Nanotechnology during my 3-year tenure at IIT Bombay, from 2007 - 2010.

Corporate Life @

1) Lead Physical design and STA engineer, Qualcomm, Bangalore India, 07/2010-04/2013

2) Lead Sales Application engineer, Cadence Design systems, Bangalore India, 04/2013-01/17

Hands on with Technology @

1) MSM (mobile station mode chips) - MSM chips are used for CDMA modulation/demodulation. It consists of DSP’s and microprocessors for running applications such as web-browsing, video conferencing, multimedia services, etc.

2) Memory test chips - Memory test chips are used to validate functionality of 28nm custom/compiler memory as well as characterize their timing, power and yield.

3) DDR-PHY test chips - DDR-PHY test chips are basically tested for high speed data transfer

4) Timing and physical design Flow development for 130nm MOSFET technology node till 16nm FinFET technology node.

5) “IR aware STAandLow power STA

6) Analyzed STA engine behavior for design size up to 850 million instance count


1) Research Assistant to Prof. Richard Pinto and Prof. Anil Kottantharayil on “Sub-100nm optimization using Electron Beam Lithography”, which intended to optimize RAITH-150TWO Electron Beam Lithography tool and the process conditions to attain minimum resolution, use the mix-and-match capabilities of the tool for sub-100nm MOSFET fabrication and generate mask plates for feature sizes above 500nm.

2) Research Assistant to with Prof. Madhav Desai, to characterize RTL, generated from C-to-RTL AHIR compiler, in terms of power, performance and area. This was done by passing RTL, generated from AHIR compiler, through standard ASIC tool chain like synthesis and place & route. The resulting netlist out of PNR was characterized using standard software


1) “A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems” submitted in the conference “13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France

2) Concurrent + Distributed MMMC STA for 'N' views

3) Signoff Timing and Leakage Optimization On 18M Instance Count Design With 8000 Clocks and Replicated Modules Using Master Clone Methodology With EDI Cockpit

4) Placement-aware ECO Methodology - No Slacking on Slack

Online Presence - Courses on Udemy

Now, to be really successful in the field of VLSI and Semiconductors, you need to take the courses in below order:

1) VSD - Physical design flow

2) VSD - Clock tree synthesis - Part 1 & 2

3) VSD - Signal Integrity

4) VSD - Static timing analysis - Part 1 & 2 (Can be taken in between)

5) VSD - Circuit design and SPICE simulations Part 1 & Part 2 (This is the core of VLSI, so you can take it in beginning or end)

6) VLSI - Essential concepts and detailed interview guide (This course is a glimpse of all above courses, but for details of each topic, you need to take course 1) to 5).)

7) VSD - Custom Layout (Can be taken in between) 

8) VSD - Library characterization and modelling - Part 1 (STA-1 and 2, Circuit design and SPICE simulations-1 and 2 are mandatory)

Connect with me for more guidance !!

Hope you enjoy the session best of luck for future !!