VSD - Physical Design Flow
4.3 (344 ratings)
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VSD - Physical Design Flow

VLSI - Building a chip is like building a city!!
Bestselling
4.3 (344 ratings)
Instead of using a simple lifetime average, Udemy calculates a course's star rating by considering a number of different factors such as the number of ratings, the age of ratings, and the likelihood of fraudulent ratings.
2,501 students enrolled
Created by Kunal Ghosh
Last updated 3/2015
English
Current price: $10 Original price: $95 Discount: 89% off
5 hours left at this price!
30-Day Money-Back Guarantee
Includes:
  • 5 hours on-demand video
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
What Will I Learn?
  • Understand Industrial Physical Design Flow
  • Modify and Develop own Flow as per Specifications
View Curriculum
Requirements
  • Basic Digital Design
Description

The course is designed in the form of micro-videos, which delivers content in the form of Info-Graphics. It is designed for self-learning and will help to polish the Industrial skills in VLSI World. This course will cover end-to-end description from basic Device Physics to Chip Design.

We have contributed anonymously to this website, just to share the part of knowledge learned all these years, with the students keen to learn the basic concepts of the Chip Design. And also shared our industrial experience to give the technological exposure of current development in chip world...

Who is the target audience?
  • Students looking for entry in VLSI World and explore new ways of solving problems
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Curriculum For This Course
30 Lectures
04:44:39
+
Floorplanning
5 Lectures 48:45
Utilization Factor And Aspect Ratio
09:10

Concept Of Pre-Placed Cells
09:27

De-coupling Capacitors
10:08

Power Planning
10:26

Pin Placement And Logical Cell Placement Blockage
09:34
+
Placement
3 Lectures 28:12
Net-list Binding And Placement
09:22

Optimize Placement Using Estimated Wire Length And Capacitance
10:02

Optimize Placement Conitnued
08:48
+
Timing Analysis With Ideal Clocks
5 Lectures 45:24
Setup Timing Analysis And Introduction to Flip-Flop Setup Time
09:44

Introduction To Clock Jitter and Uncertainty
08:24

Setup Timing Analysis with Multiple Clocks
08:49

Multiple Clock Timing Analysis And Introduction To Data Slew Check
09:06

Data Slew Check
09:21
+
Clock Tree Synthesis And Signal Integrity
5 Lectures 49:17
Clock Tree Routing And Buffering using H-Tree Algorithm
09:07

Crosstalk And Clock Net Shielding
09:24

Static Timing Analysis With Real Clocks
12:18

Hold Timing Analysis Concluded
10:11

Multiple Clocks Setup Timing Analysis With Real Clocks
08:17
+
Routing And Design Rule Check (DRC)
3 Lectures 28:27
Introduction to Maze Routing - Lee's Algorithm
08:42

Lee's Algorithm Conclusion
09:52

Design Rule Check
09:53
+
Parasitics Extraction
4 Lectures 35:51
Introduction to IEEE 1481 - 1999 SPEF format
09:20

SPEF Representation of a NET
08:15

Distributed Resistance And Capacitance Representation in SPEF
09:54

SPEF Header Description, Physical Design Flow Conclusion and What Next !!
08:22
About the Instructor
Kunal Ghosh
4.3 Average rating
1,703 Reviews
12,616 Students
14 Courses
Digital and Sign-off expert at VLSI System Design(VSD)

I received MTech Degree in Department of Electrical Engineering (EE) from Indian Institute of Technology (IIT) Bombay in 2010 and specialized in VLSI Design & Nanotechnology during my 3-year tenure at IIT Bombay, from 2007 - 2010.

Corporate Life @

1) Lead Physical design and STA engineer, Qualcomm, Bangalore India, 07/2010-04/2013

2) Lead Sales Application engineer, Cadence Design systems, Bangalore India, 04/2013-01/17

Hands on with Technology @

1) MSM (mobile station mode chips) - MSM chips are used for CDMA modulation/demodulation. It consists of DSP’s and microprocessors for running applications such as web-browsing, video conferencing, multimedia services, etc.

2) Memory test chips - Memory test chips are used to validate functionality of 28nm custom/compiler memory as well as characterize their timing, power and yield.

3) DDR-PHY test chips - DDR-PHY test chips are basically tested for high speed data transfer

4) Timing and physical design Flow development for 130nm MOSFET technology node till 16nm FinFET technology node.

5) “IR aware STAandLow power STA

6) Analyzed STA engine behavior for design size up to 850 million instance count

ACADEMIC

1) Research Assistant to Prof. Richard Pinto and Prof. Anil Kottantharayil on “Sub-100nm optimization using Electron Beam Lithography”, which intended to optimize RAITH-150TWO Electron Beam Lithography tool and the process conditions to attain minimum resolution, use the mix-and-match capabilities of the tool for sub-100nm MOSFET fabrication and generate mask plates for feature sizes above 500nm.

2) Research Assistant to with Prof. Madhav Desai, to characterize RTL, generated from C-to-RTL AHIR compiler, in terms of power, performance and area. This was done by passing RTL, generated from AHIR compiler, through standard ASIC tool chain like synthesis and place & route. The resulting netlist out of PNR was characterized using standard software

PUBLICATION 

1) “A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems” submitted in the conference “13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France

2) Concurrent + Distributed MMMC STA for 'N' views

3) Signoff Timing and Leakage Optimization On 18M Instance Count Design With 8000 Clocks and Replicated Modules Using Master Clone Methodology With EDI Cockpit

4) Placement-aware ECO Methodology - No Slacking on Slack

Online Presence - Courses on Udemy

Now, to be really successful in the field of VLSI and Semiconductors, you need to take the courses in below order:

1) VSD - Physical design flow

2) VSD - Clock tree synthesis - Part 1 & 2

3) VSD - Signal Integrity

4) VSD - Static timing analysis - Part 1 & 2 (Can be taken in between)

5) VSD - Circuit design and SPICE simulations Part 1 & Part 2 (This is the core of VLSI, so you can take it in beginning or end)

6) VLSI - Essential concepts and detailed interview guide (This course is a glimpse of all above courses, but for details of each topic, you need to take course 1) to 5).)

7) VSD - Custom Layout (Can be taken in between) 

8) VSD - Library characterization and modelling - Part 1 (STA-1 and 2, Circuit design and SPICE simulations-1 and 2 are mandatory)

Connect with me for more guidance !!

Hope you enjoy the session best of luck for future !!