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The course is designed in the form of micro-videos, which delivers content in the form of Info-Graphics. It is designed for self-learning and will help to polish the Industrial skills in VLSI World. This course will cover end-to-end description from basic Device Physics to Chip Design.
We have contributed anonymously to this website, just to share the part of knowledge learned all these years, with the students keen to learn the basic concepts of the Chip Design. And also shared our industrial experience to give the technological exposure of current development in chip world...
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|Section 1: Physical Design Flow Overview|
Netlist Binding And Placement OptimizationPreview
Placement Timing And Clock Tree SynthesisPreview
Clock Net ShieldingPreview
Route - DRC Clean - Parasitics Extraction - Final STAPreview
|Section 2: Floorplanning|
Utilization Factor And Aspect Ratio
Concept Of Pre-Placed Cells
Pin Placement And Logical Cell Placement Blockage
|Section 3: Placement|
Net-list Binding And Placement
Optimize Placement Using Estimated Wire Length And Capacitance
Optimize Placement Conitnued
|Section 4: Timing Analysis With Ideal Clocks|
Setup Timing Analysis And Introduction to Flip-Flop Setup Time
Introduction To Clock Jitter and Uncertainty
Setup Timing Analysis with Multiple Clocks
Multiple Clock Timing Analysis And Introduction To Data Slew Check
Data Slew Check
|Section 5: Clock Tree Synthesis And Signal Integrity|
Clock Tree Routing And Buffering using H-Tree Algorithm
Crosstalk And Clock Net Shielding
Static Timing Analysis With Real Clocks
Hold Timing Analysis Concluded
Multiple Clocks Setup Timing Analysis With Real Clocks
|Section 6: Routing And Design Rule Check (DRC)|
Introduction to Maze Routing - Lee's Algorithm
Lee's Algorithm Conclusion
Design Rule Check
|Section 7: Parasitics Extraction|
Introduction to IEEE 1481 - 1999 SPEF format
SPEF Representation of a NET
Distributed Resistance And Capacitance Representation in SPEF
SPEF Header Description, Physical Design Flow Conclusion and What Next !!
As a 'Growth Hacker', I intend to help students/professionals build their profile even stronger in semiconductors and VLSI, by creating courses at every possible domain in Back end. The experiments which I perform in VSD courses using open-source EDA tools, are of similar complexity of current chip design industry. Till date I have nurtured around 10000+ students and professionals through videos and many of them have been placed or moved to leading semiconductor industries. I have been doing this part time for past 6 years, and now doing this full time at VSD. Happy Learning!!
Now, to be really successful in the field of VLSI and Semiconductors, you need to take the courses in below order:
1) VSD - Physical design flow
2) VSD - Clock tree synthesis - Part 1 & 2
3) VSD - Signal Integrity
4) VSD - Static timing analysis - Part 1 & 2 (Can be taken in between)
5) VSD - Circuit design and SPICE simulations Part 1 & Part 2 (This is the core of VLSI, so you can take it in beginning or end)
6) VLSI - Essential concepts and detailed interview guide (This course is a glimpse of all above courses, but for details of each topic, you need to take course 1) to 5).)
7) VSD - Custom Layout (Can be taken in between)
Connect with me for more guidance !!
Hope you enjoy the session best of luck for future !!