VSD - Library characterization and modelling - Part 1
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VSD - Library characterization and modelling - Part 1

VLSI - The heart of STA, PNR, CTS and Crosstalk
4.5 (45 ratings)
Instead of using a simple lifetime average, Udemy calculates a course's star rating by considering a number of different factors such as the number of ratings, the age of ratings, and the likelihood of fraudulent ratings.
288 students enrolled
Created by Kunal Ghosh
Last updated 5/2017
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Current price: $10 Original price: $95 Discount: 89% off
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  • 5 hours on-demand video
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
What Will I Learn?
  • Understand timing, noise and power libraries syntax and semantics
  • Develop models for logic gates and macros
  • Use the above generated models and do STA
View Curriculum
  • Full knowledge on circuit design and SPICE simulations
  • Full knowledge on custom layout
  • Nice to have knowledge on Physical design, Static timing analysis, Noise & Crosstalk and Clock tree synthesis
  • You can refer to my existing courses or any other external material, but knowledge about above all is a must

If you are STA engineer or PNR engineer or CTS engineer or, in general, a physical designer or Synthesis engineer, you must have definitely come across the word 'Library'. This course explains you, in detail, what it exactly means. 

You can call Library as the soul and heart of Semiconductor industries. Without them, you can't have single chip out. Without the knowledge of Libraries, all other courses are incomplete. 

Guess what, you are at the right page. This course gives a comprehensive overview of characterization techniques and advanced modelling of circuits for modern and advanced nodes. 

Not only that, you will see what goes behind designing a simple single input inverter. The gates like inverter, buffer, AND, OR are all called as cell, and you will be amazed to see how are the represented in real IC design.

This course is designed in collaboration with leading characterization company Paripath, who have designed the state-of-the-art characterization software called GUNA

I would like to Thank complete Paripath team for helping me in designing experiments for this course. This course is motivated by desire to fill gap on characterization and modelling


Liberty is a registered trademark of Synopsys Inc.

Verilog is a registered trademark of Cadence Design Systems, Inc.

SDF and SPEF are trademarks of Open Verilog International

Get in right now and have an unforgettable journey of your life...

Happy Learning!!

Who is the target audience?
  • Research professionals
  • Graduate students
  • Circuit and PDK designers
  • Characterization engineers
  • CAD developers
  • Managers, Mentors and the merely curious
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Curriculum For This Course
39 Lectures
2 Lectures 07:14

Need for characterization
Cell design and characterization flows
4 Lectures 29:09

Circuit design step

Layout design step

Typical characterization flow
General Timing characterization parameters
5 Lectures 37:48
Timing threshold definitions

Propagation delay and transition time

Output voltage waveform and introduction to tristate buffer

Different transitions for tristate buffer
Timing characterization parameters for registers
5 Lectures 32:51
Netlist connectivity for latch and flipflop

Library setup time as a function of data and clock transition time

Library setup time for TSPC register

Hold time, recovery & removal time evaluation
Noise characterization and modelling
7 Lectures 59:34
Introduction to noise - Crosstalk glitch and delta delay

ccsn_first_stage, ccsn_last_stage and VIVO model based dc_current

Need of dc_current attribute

Noise immunity curve, propagated_noise_high and propagated_noise_low

stage_type attribute and need for tie_hi cells

Miller cap, arc based ccs noise model and full noise library
Power characterization and modelling
8 Lectures 01:03:23
Static power - Subthreshold current and junction leakage current

Static power - Tunnelling current

Internal leakage power - leakage_current and leakage_power groups

Dynamic power - Switching current

Dynamic power - Short-circuit current

Switching power and short-circuit power modelling

Hidden power concept and modelling
Timing modelling
7 Lectures 55:07
Groups and attributes

Library group and its attributes

Cell groups and combinational function pin groups

Flip-flop modelling using 'ff' group

Latch modelling using 'latch' group

Flip-flop modelling using 'statetable' group and introduction to 'driver model'
1 Lecture 08:55
Driver model, receiver model and conclusion
About the Instructor
Kunal Ghosh
4.3 Average rating
1,717 Reviews
12,679 Students
14 Courses
Digital and Sign-off expert at VLSI System Design(VSD)

I received MTech Degree in Department of Electrical Engineering (EE) from Indian Institute of Technology (IIT) Bombay in 2010 and specialized in VLSI Design & Nanotechnology during my 3-year tenure at IIT Bombay, from 2007 - 2010.

Corporate Life @

1) Lead Physical design and STA engineer, Qualcomm, Bangalore India, 07/2010-04/2013

2) Lead Sales Application engineer, Cadence Design systems, Bangalore India, 04/2013-01/17

Hands on with Technology @

1) MSM (mobile station mode chips) - MSM chips are used for CDMA modulation/demodulation. It consists of DSP’s and microprocessors for running applications such as web-browsing, video conferencing, multimedia services, etc.

2) Memory test chips - Memory test chips are used to validate functionality of 28nm custom/compiler memory as well as characterize their timing, power and yield.

3) DDR-PHY test chips - DDR-PHY test chips are basically tested for high speed data transfer

4) Timing and physical design Flow development for 130nm MOSFET technology node till 16nm FinFET technology node.

5) “IR aware STAandLow power STA

6) Analyzed STA engine behavior for design size up to 850 million instance count


1) Research Assistant to Prof. Richard Pinto and Prof. Anil Kottantharayil on “Sub-100nm optimization using Electron Beam Lithography”, which intended to optimize RAITH-150TWO Electron Beam Lithography tool and the process conditions to attain minimum resolution, use the mix-and-match capabilities of the tool for sub-100nm MOSFET fabrication and generate mask plates for feature sizes above 500nm.

2) Research Assistant to with Prof. Madhav Desai, to characterize RTL, generated from C-to-RTL AHIR compiler, in terms of power, performance and area. This was done by passing RTL, generated from AHIR compiler, through standard ASIC tool chain like synthesis and place & route. The resulting netlist out of PNR was characterized using standard software


1) “A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems” submitted in the conference “13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France

2) Concurrent + Distributed MMMC STA for 'N' views

3) Signoff Timing and Leakage Optimization On 18M Instance Count Design With 8000 Clocks and Replicated Modules Using Master Clone Methodology With EDI Cockpit

4) Placement-aware ECO Methodology - No Slacking on Slack

Online Presence - Courses on Udemy

Now, to be really successful in the field of VLSI and Semiconductors, you need to take the courses in below order:

1) VSD - Physical design flow

2) VSD - Clock tree synthesis - Part 1 & 2

3) VSD - Signal Integrity

4) VSD - Static timing analysis - Part 1 & 2 (Can be taken in between)

5) VSD - Circuit design and SPICE simulations Part 1 & Part 2 (This is the core of VLSI, so you can take it in beginning or end)

6) VLSI - Essential concepts and detailed interview guide (This course is a glimpse of all above courses, but for details of each topic, you need to take course 1) to 5).)

7) VSD - Custom Layout (Can be taken in between) 

8) VSD - Library characterization and modelling - Part 1 (STA-1 and 2, Circuit design and SPICE simulations-1 and 2 are mandatory)

Connect with me for more guidance !!

Hope you enjoy the session best of luck for future !!