VSD - Library characterization and modelling - Part 1

Explore how the library stores standard cells with varying functions, sizes, and voltages, and how drc rules, spice models, and foundry design kits guide the cell design flow.

Explore how user defined actions in library design set power, timing, and pin location, and learn the circuit design and layout steps to meet supply voltage and noise margins.

Explore layout design steps from transistor-level function to stick diagram and polysilicon placement. Convert diagrams to layout under DRC rules, then extract parasitics and timing for fabrication.

Follow the typical characterization flow to read models, interpret extracted spice netlists, manage subcircuits, apply stimuli, and assess buffer timing and power characteristics.

Define timing threshold concepts for digital signals, including rise and fall definitions, input and output relationships, and 50 percent threshold based delay calculations.

Explore propagation delay and transition time in digital circuits, using 50 percent thresholds to compare rise and fall times, calculate delays, and identify causes of negative or unexpected delays.

Explore how to derive delays using the CCS timing model by analyzing the output current of a buffer, its output capacitance, and input transitions.

Analyze the output voltage waveform and tristate buffer concepts, examining how capacitances influence voltage and current, with emphasis on model formats and high-impedance states for memory bus applications.

Explore how a tristate buffer transitions between high impedance and logic levels. Learn how enable and nibble signals govern input and output behavior.

Explore netlist connectivity for latch and flip-flop by examining set up time, clock polarity, negative and positive latches, and muxed paths.

Explore how library setup time depends on data and clock transition, calibrating setup times for flip flop and multiplexers, using SPICE simulations to ensure reliable data capture.

Explore true single phase clocked (TSPC) registers and hold time evaluation, comparing dynamic sequencing with static designs and analyzing hold and setup times around clock edges.

Explore the setup and hold times of a TSPC register, analyzing clock edges, input stability, and how the D flip-flop captures data.

Analyze hold time, recovery time, and removal time for a register, focusing on input setup and clock rising edge effects on data capture and output stability.

Explore cross-talk glitches from mutual coupling capacitance between aggressor and victim nets, causing memory resets and data delays that impact clock signals, delta delay, and skew.

Characterize and model channel connected components (CCC) in the library by analyzing inverters, transmission gates, and flip-flops, including clocking and noise characterization.

Explore ccsn first stage, ccsn last stage, and vivo model based dc current for library characterization, detailing input/output pin behavior, inverter operation, and dc current extraction via voltage sweeps.

Investigate how the dc_current attribute captures dc current noise and informs timing in library characterization, using CCN_lookup_table concepts and current-based models.

Investigate noise and noise immunity using an inverter as a channel, examining aggressor and victim interactions, mutual coupling, and the propagated_noise_high and propagated_noise_low phenomena via a noise lookup table.

Explain the stage_type attribute and the need for tie_hi cells to deliver a clean logic one under power-supply variations and noise, with spice simulations.

Explore Miller cap and Miller effect, arc-based ccs noise models, and a full noise library; analyze coupling and overlap capacitances, input-output feedback, and spice-based noise simulations for small-gate designs.

Explore static power through subthreshold and junction leakage currents that drive off-state dissipation. See how bias, doping, and junction area influence leakage and delay in transistor design.

Explore gate leakage current and tunneling in MOS capacitor structures, using energy band diagrams to explain conduction, valence and intrinsic leakage, junction leakage, and related materials in semiconductors.

Discover how leakage current and leakage power are modeled in the leakage group, including static current and clock and input scenarios, with unit handling in timing libraries.

Analyze cell leakage power and gate leakage, showing how input states determine leakage currents, and contrast static leakage with dynamic switching power.

Explore dynamic power and switching current in logic, modeling charging and discharging currents, output switching, and short-circuit power as a function of input transitions and load capacitance.

Explore dynamic power and short-circuit current by examining how gate-to-source voltage crosses transistor thresholds during logic transitions, and how output capacitor, load, and switching speed shape discharge current.

Explore how switching power and short-circuit power are modeled, including energy calculation from power, timing considerations, and indexing tables for input slew and output capacitance.

Analyze hidden power in digital circuits through nand gate and inverter behavior, explore static and dynamic power, and learn input-driven modeling approaches for timing.

Explore the Liberty library format, including groups, cells, pins, and attributes, and learn how to model timing, power, and open group concepts for the VSD library characterization.

Explore common library records and how data sit in lookup tables with indexed access. Learn to interpret delay and capacitance, input/output thresholds, and slew-related ranges expressed in nanoseconds.

Learn how cell groups and pin groups underpin combinational function design, including inverters, buffers, and power pins, and explore sequences of functions like latch, memory, and flip-flops.

Explore how to model flip-flops using an 'ff' group, including clock, reset, preset, and active signals, and compare flip-flop group versus state table approaches.

Explore latch modelling using the latch group and learn how flip-flops and latches are described with state tables, clock or data inputs, and next-state logic.

Map a finite state machine to a statetable, a lookup table with inputs and the current state. Define next state and output and relate to latch and flip-flop behavior.

Delve into flip-flop modelling with the statetable group and introduce the driver model, detailing state tables, clock edges, and active-low resets that govern D-flip-flop behavior.

Explore driver and receiver models within library-based timing, detailing input and output capacitances, 20-80% transitions, 50% delay threshold, and how varying capacitance shapes timing accuracy.