VSD - Library characterization and modelling - Part 1

VLSI - The heart of STA, PNR, CTS and Crosstalk

Created byKunal Ghosh

Last updated 5/2017

English

What you'll learn

Understand timing, noise and power libraries syntax and semantics
Develop models for logic gates and macros
Use the above generated models and do STA

Course content

8 sections • 39 lectures • 4h 54m total length

Introduction and Acknowledgements1:06
Need for characterization6:08

Introduction to noise - Crosstalk glitch and delta delay7:22
Introduction to channel connected components (CCC)8:17
ccsn_first_stage, ccsn_last_stage and VIVO model based dc_current8:22
Need of dc_current attribute5:24
Noise immunity curve, propagated_noise_high and propagated_noise_low10:40
stage_type attribute and need for tie_hi cells8:47
Miller cap, arc based ccs noise model and full noise library10:42

Static power - Subthreshold current and junction leakage current8:35
Static power - Tunnelling current8:36
Internal leakage power - leakage_current and leakage_power groups8:27
Internal leakage power - cell_leakage_power & Tunneling curent - gate_leakage8:05
Dynamic power - Switching current6:38
Dynamic power - Short-circuit current8:27
Switching power and short-circuit power modelling6:35
Hidden power concept and modelling8:00

Requirements

Full knowledge on circuit design and SPICE simulations
Full knowledge on custom layout
Nice to have knowledge on Physical design, Static timing analysis, Noise & Crosstalk and Clock tree synthesis
You can refer to my existing courses or any other external material, but knowledge about above all is a must

Description

If you are STA engineer or PNR engineer or CTS engineer or, in general, a physical designer or Synthesis engineer, you must have definitely come across the word 'Library'. This course explains you, in detail, what it exactly means.

You can call Library as the soul and heart of Semiconductor industries. Without them, you can't have single chip out. Without the knowledge of Libraries, all other courses are incomplete.

Guess what, you are at the right page. This course gives a comprehensive overview of characterization techniques and advanced modelling of circuits for modern and advanced nodes.

Not only that, you will see what goes behind designing a simple single input inverter. The gates like inverter, buffer, AND, OR are all called as cell, and you will be amazed to see how are the represented in real IC design.

This course is designed in collaboration with leading characterization company Paripath, who have designed the state-of-the-art characterization software called GUNA

I would like to Thank complete Paripath team for helping me in designing experiments for this course. This course is motivated by desire to fill gap on characterization and modelling

Trademark:

Liberty is a registered trademark of Synopsys Inc.

Verilog is a registered trademark of Cadence Design Systems, Inc.

SDF and SPEF are trademarks of Open Verilog International

Get in right now and have an unforgettable journey of your life...

Happy Learning!!

Who this course is for:

Research professionals
Graduate students
Circuit and PDK designers
Characterization engineers
CAD developers
Managers, Mentors and the merely curious

VSD - Library characterization and modelling - Part 1

What you'll learn

Explore related topics

Course content

Introduction2 lectures • 7min

Cell design and characterization flows4 lectures • 29min

General Timing characterization parameters5 lectures • 38min

Timing characterization parameters for registers5 lectures • 33min

Noise characterization and modelling7 lectures • 1hr

Power characterization and modelling8 lectures • 1hr 3min

Timing modelling7 lectures • 55min

Conclusion1 lecture • 9min

Requirements

Description

Who this course is for: