VSD - Custom Layout

VLSI - This is where design meets fabrication

Created byKunal Ghosh

Last updated 1/2017

English

What you'll learn

Draw layout from scratch, i.e. right from tech files to metal layer
Understand each and every mask level, through appropriate fabrication steps
Get to know how physical design flow communicates with CMOS fabrication process
This is how 2 different industries communicate

Course content

7 sections • 36 lectures • 4h 43m total length

Course content4:31

Create active regions9:47
Formation of N-well and P-well6:20
Formation of gate terminal8:07
Learn the fabrication steps to form a gate terminal in VSD custom layout, including controlling gate oxide, doping concentration, and polysilicon gate through deposition, implantation, and etching.
Lightly doped drain (LDD) formation7:16
Source drain formation4:24
Local interconnect formation6:35
Build contacts by etching the rim and exposing gate, source, and drain to enable local interconnect formation through sputtering of high-resistivity material.
Higher level metal formation8:47

INV.mag0:47
min2.tech3:30
Corner stitching introduction10:05
Explore how magic represents fabrication data as non-overlapping cells through corner stitching, using magic and tech files to model planes, solids, and space coordinates.
Corner stitch to planes to tiles7:26
Explore how planes and tiles form the model plane and active plane, showing overlaps, substrate-metal contacts, diffusion, and coordinates that map active areas.
Active tile types and tech file content10:00
Contacts and styles8:08
Connect section for circuit extraction9:36

Introduction to DRC and lambda design rules9:51
Poly extension and poly to diffusion spacing rules10:31
Poly to diffusion spacing and diffusion contact width rules8:19
Metal1 width and poly to metal1 spacing rules5:50
Contact spacing and minimum active width rules8:34
From logic to layout to SPICE9:03
Extract parasitics from the most logical load, generate SPICE netlists, and run SPICE simulations to compare delay and behavior against ideal definitions, guiding layout decisions.

Introduction to simple path, euler's path and euler's circuit9:51
Introduction to stick diagram10:28
Learn how to create a stick diagram for CMOS layouts by converting transistors into diffusion sticks (red/green), polysilicon gates (red), and blue power rails (vdd/vss), with diffusion contacts and DRC.
Derive actual dimension from stick diagram9:46
Derive the actual dimensions from the stick diagram by defining polysilicon and active regions, their extensions, and spacing, then validate with drc rules and lambda values.

Pre-layout simulation9:17
Layout using 'only' stick diagram9:32
Euler's path for Fn - Input gate ordering7:17
Explore constructing Euler's path for Fn by input gate ordering in a MOS transistor layout, arranging polysilicon inputs to cover every edge and optimize the circuit.
Improved stick diagram for new gate input ordering8:34
Abstract layout from stick diagram9:38
Derive actual dimension for Fn10:02
Script to create layout9:49
draw_fn.tcl0:51
Final layout and input/output labelling10:46

Requirements

Basic terms of CMOS, NMOS, PMOS
A brief summary of my existing course on 'Circuit design and SPICE simulations' will help, but can do even without that course
A brief knowledge of my existing courses on physical design flow and static timing analysis will also help

Description

Physical designers and CMOS fabrication team communicates with each other, and this course says it 'How?'

While physical designers use all the outputs from experiments performed by fabrication department, this course will demonstrate the best of both worlds and connect them through exchange of certain files in certain format

This way, custom layout designers get to know an insight how does fabrication works, fabrication engineers get to know, how layout engineers uses their information. So this course is a place where both meet, talk and connect.

Also, the standard files needed to draw and simulate layout, are being taken, deduced and created from scratch and on the fly. This is, by far, the best way to understand layout, and I can promise you an exciting journey throughout this course

Course is structured to explain the CMOS packaging and fabrication steps in beginning, followed by software and files used to draw and simulate layout, and look into DRC rules.

Next, we will take a simple CMOS inverter and apply all concepts learned above. Finally, we will learn the 'Art of layout' using Euler's path. This is where you will solve complex functions and draw a layout out of it.

Welcome you all to my course and Happy Learning!!

See you in class!

Who this course is for:

Anyone curious to know the inception of layout
Anyone curious to know the software behind layout drawing
Anyone who wants to know how chip designers talk with chip fabrication department

VSD - Custom Layout

What you'll learn

Explore related topics

Course content

Introduction1 lecture • 5min

Inception of layout - CMOS fabrication process7 lectures • 51min

Introduction to ‘corner stitching’ and ‘tech files’7 lectures • 50min

Design rule checking (DRC)6 lectures • 52min

Introduction to euler's path and stick diagram3 lectures • 30min

Art of layout using Euler's path plus Stick diagram9 lectures • 1hr 16min

Conclusion, acknowledgements and what next!!!3 lectures • 10min

Requirements

Description

Who this course is for: