VSD - Custom Layout
4.9 (45 ratings)
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VSD - Custom Layout

VLSI - This is where design meets fabrication
4.9 (45 ratings)
Instead of using a simple lifetime average, Udemy calculates a course's star rating by considering a number of different factors such as the number of ratings, the age of ratings, and the likelihood of fraudulent ratings.
332 students enrolled
Created by Kunal Ghosh
Last updated 11/2016
Current price: $10 Original price: $95 Discount: 89% off
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  • 4.5 hours on-demand video
  • 5 Articles
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
What Will I Learn?
  • Draw layout from scratch, i.e. right from tech files to metal layer
  • Understand each and every mask level, through appropriate fabrication steps
  • Get to know how physical design flow communicates with CMOS fabrication process
  • This is how 2 different industries communicate
View Curriculum
  • Basic terms of CMOS, NMOS, PMOS
  • A brief summary of my existing course on 'Circuit design and SPICE simulations' will help, but can do even without that course
  • A brief knowledge of my existing courses on physical design flow and static timing analysis will also help

Physical designers and CMOS fabrication team communicates with each other, and this course says it 'How?'

While physical designers use all the outputs from experiments performed by fabrication department, this course will demonstrate the best of both worlds and connect them through exchange of certain files in certain format

This way, custom layout designers get to know an insight how does fabrication works, fabrication engineers get to know, how layout engineers uses their information. So this course is a place where both meet, talk and connect. 

Also, the standard files needed to draw and simulate layout, are being taken, deduced and created from scratch and on the fly. This is, by far, the best way to understand layout, and I can promise you an exciting journey throughout this course

Course is structured to explain the CMOS packaging and fabrication steps in beginning, followed by software and files used to draw and simulate layout, and look into DRC rules.

Next, we will take a simple CMOS inverter and apply all concepts learned above. Finally, we will learn the 'Art of layout' using Euler's path. This is where you will solve complex functions and draw a layout out of it. 

Welcome you all to my course and Happy Learning!!

See you in class!

Who is the target audience?
  • Anyone curious to know the inception of layout
  • Anyone curious to know the software behind layout drawing
  • Anyone who wants to know how chip designers talk with chip fabrication department
Compare to Other VLSI Courses
Curriculum For This Course
36 Lectures
1 Lecture 04:31
Inception of layout - CMOS fabrication process
7 Lectures 51:16
Create active regions

Formation of gate terminal

Lightly doped drain (LDD) formation

Source drain formation

Local interconnect formation

Higher level metal formation
Introduction to ‘corner stitching’ and ‘tech files’
7 Lectures 49:57

Corner stitching introduction

Corner stitch to planes to tiles

Active tile types and tech file content

Contacts and styles

Connect section for circuit extraction
Design rule checking (DRC)
6 Lectures 52:08
Introduction to DRC and lambda design rules

Poly to diffusion spacing and diffusion contact width rules

Metal1 width and poly to metal1 spacing rules

Contact spacing and minimum active width rules

From logic to layout to SPICE
Introduction to euler's path and stick diagram
3 Lectures 30:05
Introduction to simple path, euler's path and euler's circuit

Introduction to stick diagram

Derive actual dimension from stick diagram
Art of layout using Euler's path plus Stick diagram
9 Lectures 01:15:47
Pre-layout simulation

Layout using 'only' stick diagram

Improved stick diagram for new gate input ordering

Abstract layout from stick diagram

Derive actual dimension for Fn

Script to create layout

Conclusion, acknowledgements and what next!!!
3 Lectures 10:11

Post-layout simulation and conclusion
About the Instructor
Kunal Ghosh
4.4 Average rating
1,895 Reviews
13,252 Students
15 Courses
Digital and Sign-off expert at VLSI System Design(VSD)

I received MTech Degree in Department of Electrical Engineering (EE) from Indian Institute of Technology (IIT) Bombay in 2010 and specialized in VLSI Design & Nanotechnology during my 3-year tenure at IIT Bombay, from 2007 - 2010.

Corporate Life @

1) Lead Physical design and STA engineer, Qualcomm, Bangalore India, 07/2010-04/2013

2) Lead Sales Application engineer, Cadence Design systems, Bangalore India, 04/2013-01/17

Hands on with Technology @

1) MSM (mobile station mode chips) - MSM chips are used for CDMA modulation/demodulation. It consists of DSP’s and microprocessors for running applications such as web-browsing, video conferencing, multimedia services, etc.

2) Memory test chips - Memory test chips are used to validate functionality of 28nm custom/compiler memory as well as characterize their timing, power and yield.

3) DDR-PHY test chips - DDR-PHY test chips are basically tested for high speed data transfer

4) Timing and physical design Flow development for 130nm MOSFET technology node till 16nm FinFET technology node.

5) “IR aware STAandLow power STA

6) Analyzed STA engine behavior for design size up to 850 million instance count


1) Research Assistant to Prof. Richard Pinto and Prof. Anil Kottantharayil on “Sub-100nm optimization using Electron Beam Lithography”, which intended to optimize RAITH-150TWO Electron Beam Lithography tool and the process conditions to attain minimum resolution, use the mix-and-match capabilities of the tool for sub-100nm MOSFET fabrication and generate mask plates for feature sizes above 500nm.

2) Research Assistant to with Prof. Madhav Desai, to characterize RTL, generated from C-to-RTL AHIR compiler, in terms of power, performance and area. This was done by passing RTL, generated from AHIR compiler, through standard ASIC tool chain like synthesis and place & route. The resulting netlist out of PNR was characterized using standard software


1) “A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems” submitted in the conference “13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France

2) Concurrent + Distributed MMMC STA for 'N' views

3) Signoff Timing and Leakage Optimization On 18M Instance Count Design With 8000 Clocks and Replicated Modules Using Master Clone Methodology With EDI Cockpit

4) Placement-aware ECO Methodology - No Slacking on Slack

Online Presence - Courses on Udemy

Now, to be really successful in the field of VLSI and Semiconductors, you need to take the courses in below order:

1) VSD - Physical design flow

2) VSD - Clock tree synthesis - Part 1 & 2

3) VSD - Signal Integrity

4) VSD - Static timing analysis - Part 1 & 2 (Can be taken in between)

5) VSD - Circuit design and SPICE simulations Part 1 & Part 2 (This is the core of VLSI, so you can take it in beginning or end)

6) VLSI - Essential concepts and detailed interview guide (This course is a glimpse of all above courses, but for details of each topic, you need to take course 1) to 5).)

7) VSD - Custom Layout (Can be taken in between) 

8) VSD - Library characterization and modelling - Part 1 (STA-1 and 2, Circuit design and SPICE simulations-1 and 2 are mandatory)

Connect with me for more guidance !!

Hope you enjoy the session best of luck for future !!