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Performance, Power and Area are the three main pillars of the Chip Design, Crosstalk can hamper all three.
Crosstalk is the interference caused due to communication between the circuits
Lets learn to " HOW TO REDUCE CROSSTALK ? " to achieve a efficient Chip design which give the best performance, uses optimal power and in minimal Chip area.
•Reasons for Crosstalk
•Introduction to Noise Margin
•Crosstalk Glitch Example
•Factors Affecting Glitch Height
•AC Noise Margin
•Timing Window Concepts
•Impact of Crosstalk on Setup and Hold Timing
•Techniques to reduce Crosstalk
•Power Supply Noise
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|Section 1: Introduction|
|Section 2: Crosstalk - Why and How Crosstalk occurs in a CHIP ??|
High Routing Density
Dominant Lateral Capacitance
Introduction to Noise MarginPreview
Noise Margin Voltage ParametersPreview
Noise Margin Equation and SummaryPreview
Lower Supply Voltage
|Section 3: Glitch Examples And Factors Affecting Glitch Height|
Basic Crosstalk Glitch Example
Glitch Discharge With High Drive Strength NMOS Transistor
Glitch Discharge With High Drive Strength PMOS Transistor
Factors Affecting Glitch Height - Spacing
Factors Affecting Glitch Height - Aggressor Drive Strength
Factors Affecting Glitch Height - Victim Drive Strength
Factors Affecting Glitch Height - Conclusion
|Section 4: Tolerable Glitch Heights and Introduction to AC Noise Margin|
Impacts Of Glitch
Introduction to Safe and Unsafe Glitches
Tolerable Glitch Heights using DC Noise Margin
Tolerable Glitch Heights using DC Noise Margin Continued
AC Noise Margin
Impact of Load on Glitch Height
Justification of Load Impact and Conclusion
|Section 5: Timing Windows|
Single Victim Multiple Aggressors
Introduction to Timing Window
Timing Window Formation
Bucketization based on Timing Windows
Final Glitch Calculation
|Section 6: Crosstalk Delta Delay Analysis|
Crosstalk Delta Delay - Aggressor Victim Switching in Opposite Direction
Impact of Crosstalk Delta Delay on Clock Skew
Setup Timing Analysis Using Real Clocks
Impact of Crosstalk Delta Delay on Setup Timing
Crosstalk Delta Delay - Aggressor Victim Switching in Same Direction
Hold Timing Analysis Using Real Clocks
Impact of Crosstalk Delta Delay on Hold Timing
|Section 7: Noise Protection Technique|
|Section 8: Power Supply Noise And Power Mesh Solution|
Introduction To Power Supply Noise
Need of Decoupling Capacitors (DECAPS)
Power Supply Noise With Multiple Instantiations
Voltage Droop And Ground Bounce
Power Mesh Solution
|Section 9: Summary|
|Section 10: Quiz and Evaluation|
|Quiz 1||1 question|
|Quiz 2||1 question|
Which of the below scenario is correct ?
Which Scenario impacts the Victim "the least" ?
Mark Potentially Unsafe Glitches among the below !!
Identify Potentially Safe Glitches !!
|Quiz 7||1 question|
Assume DC noise Margin as 0.17 and Noise width as 0ps
What is the Setup Slack between 'A' and 'B' ? (Clock Period 'T' = 70ps)
What is Hold Slack between 'B' and 'C' ?
Kunal Ghosh, an Engineer by qualification and Educator by interest. It gives me great energy to help students to understand the Concepts of VLSI and Chip Design used in semiconductor Industry and assist them to achieve goals in Professional world. My course are product of simple Principle I follow at work, Keep it Simple and Sweet, All my lectures are full of info-graphical video, where pictures speaks louder then my words.
Now, to be really successful in the field of VLSI and Semiconductors, you need to take the courses in below order:
1) VLSI Academy - Physical design flow
2) VLSI Academy - Clock tree synthesis - Part 1 & 2
3) VLSI Academy - Signal Integrity
4) VLSI Academy - Static timing analysis (Can be taken in between)
5) VLSI Academy - Circuit design and SPICE simulations Part 1 & Part 2 (This is the core of VLSI, so you can take it in beginning or end)
6) VLSI - Essential concepts and detailed interview guide (This course is a glimpse of all above courses, but for details of each topic, you need to take course 1) to 5).)
Connect with me for more guidance !!
Hope you enjoy the session best of luck for future !!