VSD - Signal Integrity
4.1 (92 ratings)
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VSD - Signal Integrity

VLSI - Real and practical steps to build chip with minimum Signal Integrity issues!!
4.1 (92 ratings)
Instead of using a simple lifetime average, Udemy calculates a course's star rating by considering a number of different factors such as the number of ratings, the age of ratings, and the likelihood of fraudulent ratings.
691 students enrolled
Created by Kunal Ghosh
Last updated 8/2014
English
Current price: $10 Original price: $95 Discount: 89% off
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Includes:
  • 6.5 hours on-demand video
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
What Will I Learn?
  • To Learn Chip Design with minimal Crosstalk in the circuits.
  • To Design a Chip with minimal errors.
View Curriculum
Requirements
  • Basic of VLSI and Chip Design
Description

Performance, Power and Area are the three main pillars of the Chip Design, Crosstalk can hamper all three. 


Crosstalk is the interference caused due to communication between the circuits

Lets learn to " HOW TO REDUCE CROSSTALK ? " to achieve a efficient Chip design which give the best performance, uses optimal power and in minimal Chip area.

Course Details:
•Reasons for Crosstalk

•Introduction to Noise Margin

•Crosstalk Glitch Example

•Factors Affecting Glitch Height

•AC Noise Margin

•Timing Window Concepts

•Impact of Crosstalk on Setup and Hold Timing

•Techniques to reduce Crosstalk

•Power Supply Noise

Who is the target audience?
  • VLSI Engineers keen to Learn Backend of Chip Design
  • Physical Design Engineer
  • Students Learning VLSI Engineering
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Curriculum For This Course
42 Lectures
06:34:08
+
Introduction
1 Lecture 08:16
+
Crosstalk - Why and How Crosstalk occurs in a CHIP ??
6 Lectures 56:15
High Routing Density
09:55

Dominant Lateral Capacitance
09:29




Lower Supply Voltage
10:12
+
Glitch Examples And Factors Affecting Glitch Height
7 Lectures 01:08:55
Basic Crosstalk Glitch Example
09:58

Glitch Discharge With High Drive Strength NMOS Transistor
09:50

Glitch Discharge With High Drive Strength PMOS Transistor
10:16

Factors Affecting Glitch Height - Spacing
09:42

Factors Affecting Glitch Height - Aggressor Drive Strength
10:28

Factors Affecting Glitch Height - Victim Drive Strength
08:28

Factors Affecting Glitch Height - Conclusion
10:13
+
Tolerable Glitch Heights and Introduction to AC Noise Margin
7 Lectures 01:04:49
Impacts Of Glitch
10:20

Introduction to Safe and Unsafe Glitches
09:43

Tolerable Glitch Heights using DC Noise Margin
09:12

Tolerable Glitch Heights using DC Noise Margin Continued
09:03

AC Noise Margin
08:29

Impact of Load on Glitch Height
09:02

Justification of Load Impact and Conclusion
09:00
+
Timing Windows
5 Lectures 46:54
Single Victim Multiple Aggressors
09:41

Introduction to Timing Window
08:58

Timing Window Formation
09:21

Bucketization based on Timing Windows
09:28

Final Glitch Calculation
09:26
+
Crosstalk Delta Delay Analysis
7 Lectures 01:04:50
Crosstalk Delta Delay - Aggressor Victim Switching in Opposite Direction
09:16

Impact of Crosstalk Delta Delay on Clock Skew
09:42

Setup Timing Analysis Using Real Clocks
10:13

Impact of Crosstalk Delta Delay on Setup Timing
09:14

Crosstalk Delta Delay - Aggressor Victim Switching in Same Direction
08:39

Hold Timing Analysis Using Real Clocks
09:19

Impact of Crosstalk Delta Delay on Hold Timing
08:27
+
Noise Protection Technique
3 Lectures 28:45
Shielding
08:34

Spacing
09:04

Drive Strength
11:07
+
Power Supply Noise And Power Mesh Solution
5 Lectures 47:09
Introduction To Power Supply Noise
11:18

Need of Decoupling Capacitors (DECAPS)
10:54

Power Supply Noise With Multiple Instantiations
08:39

Voltage Droop And Ground Bounce
09:12

Power Mesh Solution
07:06
+
Summary
1 Lecture 08:15
Summary
08:15
+
Quiz and Evaluation
0 Lectures 00:00

Which Capacitance is dominant for 0.1um and below process
1 question

What is the NMH and NML of the below Noise Curve ?
1 question

Which of the below scenario is correct ?
1 question

Which Scenario impacts the Victim "the least" ?
1 question

Mark Potentially Unsafe Glitches among the below !!
1 question

Identify Potentially Safe Glitches !!
1 question

Assume DC noise Margin as 0.17 and Noise width as 0ps

which of below bucket/s are prone to glitch ?
1 question

What is the Setup Slack between 'A' and 'B' ? (Clock Period 'T' = 70ps)
1 question

What is Hold Slack between 'B' and 'C' ?
1 question
About the Instructor
Kunal Ghosh
4.3 Average rating
1,461 Reviews
11,633 Students
14 Courses
Digital and Sign-off expert at VLSI System Design(VSD)

I received MTech Degree in Department of Electrical Engineering (EE) from Indian Institute of Technology (IIT) Bombay in 2010 and specialized in VLSI Design & Nanotechnology during my 3-year tenure at IIT Bombay, from 2007 - 2010.

Corporate Life @

1) Lead Physical design and STA engineer, Qualcomm, Bangalore India, 07/2010-04/2013

2) Lead Sales Application engineer, Cadence Design systems, Bangalore India, 04/2013-01/17

Hands on with Technology @

1) MSM (mobile station mode chips) - MSM chips are used for CDMA modulation/demodulation. It consists of DSP’s and microprocessors for running applications such as web-browsing, video conferencing, multimedia services, etc.

2) Memory test chips - Memory test chips are used to validate functionality of 28nm custom/compiler memory as well as characterize their timing, power and yield.

3) DDR-PHY test chips - DDR-PHY test chips are basically tested for high speed data transfer

4) Timing and physical design Flow development for 130nm MOSFET technology node till 16nm FinFET technology node.

5) “IR aware STAandLow power STA

6) Analyzed STA engine behavior for design size up to 850 million instance count

ACADEMIC

1) Research Assistant to Prof. Richard Pinto and Prof. Anil Kottantharayil on “Sub-100nm optimization using Electron Beam Lithography”, which intended to optimize RAITH-150TWO Electron Beam Lithography tool and the process conditions to attain minimum resolution, use the mix-and-match capabilities of the tool for sub-100nm MOSFET fabrication and generate mask plates for feature sizes above 500nm.

2) Research Assistant to with Prof. Madhav Desai, to characterize RTL, generated from C-to-RTL AHIR compiler, in terms of power, performance and area. This was done by passing RTL, generated from AHIR compiler, through standard ASIC tool chain like synthesis and place & route. The resulting netlist out of PNR was characterized using standard software

PUBLICATION 

1) “A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems” submitted in the conference “13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France

2) Concurrent + Distributed MMMC STA for 'N' views

3) Signoff Timing and Leakage Optimization On 18M Instance Count Design With 8000 Clocks and Replicated Modules Using Master Clone Methodology With EDI Cockpit

4) Placement-aware ECO Methodology - No Slacking on Slack

Online Presence - Courses on Udemy

Now, to be really successful in the field of VLSI and Semiconductors, you need to take the courses in below order:

1) VSD - Physical design flow

2) VSD - Clock tree synthesis - Part 1 & 2

3) VSD - Signal Integrity

4) VSD - Static timing analysis - Part 1 & 2 (Can be taken in between)

5) VSD - Circuit design and SPICE simulations Part 1 & Part 2 (This is the core of VLSI, so you can take it in beginning or end)

6) VLSI - Essential concepts and detailed interview guide (This course is a glimpse of all above courses, but for details of each topic, you need to take course 1) to 5).)

7) VSD - Custom Layout (Can be taken in between) 

8) VSD - Library characterization and modelling - Part 1 (STA-1 and 2, Circuit design and SPICE simulations-1 and 2 are mandatory)

Connect with me for more guidance !!

Hope you enjoy the session best of luck for future !!