VLSI Academy - Signal Integrity

Real and practical steps to build chip with minimum Signal Integrity issues!!
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457 students enrolled
Instructed by Kunal Ghosh Design / Design Thinking
$95
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  • Lectures 42
  • Contents Video: 6.5 hours
  • Skill Level Expert Level
  • Languages English
  • Includes Lifetime access
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    Available on iOS and Android
    Certificate of Completion
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About This Course

Published 8/2014 English

Course Description

Performance, Power and Area are the three main pillars of the Chip Design, Crosstalk can hamper all three. 


Crosstalk is the interference caused due to communication between the circuits

Lets learn to " HOW TO REDUCE CROSSTALK ? " to achieve a efficient Chip design which give the best performance, uses optimal power and in minimal Chip area.

Course Details:
•Reasons for Crosstalk

•Introduction to Noise Margin

•Crosstalk Glitch Example

•Factors Affecting Glitch Height

•AC Noise Margin

•Timing Window Concepts

•Impact of Crosstalk on Setup and Hold Timing

•Techniques to reduce Crosstalk

•Power Supply Noise

What are the requirements?

  • Basic of VLSI and Chip Design

What am I going to get from this course?

  • To Learn Chip Design with minimal Crosstalk in the circuits.
  • To Design a Chip with minimal errors.

What is the target audience?

  • VLSI Engineers keen to Learn Backend of Chip Design
  • Physical Design Engineer
  • Students Learning VLSI Engineering

What you get with this course?

Not for you? No problem.
30 day money back guarantee.

Forever yours.
Lifetime access.

Learn on the go.
Desktop, iOS and Android.

Get rewarded.
Certificate of completion.

Curriculum

Section 1: Introduction
Introduction
Preview
08:16
Section 2: Crosstalk - Why and How Crosstalk occurs in a CHIP ??
High Routing Density
09:55
Dominant Lateral Capacitance
09:29
Introduction to Noise Margin
Preview
08:39
Noise Margin Voltage Parameters
Preview
08:56
Noise Margin Equation and Summary
Preview
09:04
Lower Supply Voltage
10:12
Section 3: Glitch Examples And Factors Affecting Glitch Height
Basic Crosstalk Glitch Example
09:58
Glitch Discharge With High Drive Strength NMOS Transistor
09:50
Glitch Discharge With High Drive Strength PMOS Transistor
10:16
Factors Affecting Glitch Height - Spacing
09:42
Factors Affecting Glitch Height - Aggressor Drive Strength
10:28
Factors Affecting Glitch Height - Victim Drive Strength
08:28
Factors Affecting Glitch Height - Conclusion
10:13
Section 4: Tolerable Glitch Heights and Introduction to AC Noise Margin
Impacts Of Glitch
10:20
Introduction to Safe and Unsafe Glitches
09:43
Tolerable Glitch Heights using DC Noise Margin
09:12
Tolerable Glitch Heights using DC Noise Margin Continued
09:03
AC Noise Margin
08:29
Impact of Load on Glitch Height
09:02
Justification of Load Impact and Conclusion
09:00
Section 5: Timing Windows
Single Victim Multiple Aggressors
09:41
Introduction to Timing Window
08:58
Timing Window Formation
09:21
Bucketization based on Timing Windows
09:28
Final Glitch Calculation
09:26
Section 6: Crosstalk Delta Delay Analysis
Crosstalk Delta Delay - Aggressor Victim Switching in Opposite Direction
09:16
Impact of Crosstalk Delta Delay on Clock Skew
09:42
Setup Timing Analysis Using Real Clocks
10:13
Impact of Crosstalk Delta Delay on Setup Timing
09:14
Crosstalk Delta Delay - Aggressor Victim Switching in Same Direction
08:39
Hold Timing Analysis Using Real Clocks
09:19
Impact of Crosstalk Delta Delay on Hold Timing
08:27
Section 7: Noise Protection Technique
Shielding
08:34
Spacing
09:04
Drive Strength
11:07
Section 8: Power Supply Noise And Power Mesh Solution
Introduction To Power Supply Noise
11:18
Need of Decoupling Capacitors (DECAPS)
10:54
Power Supply Noise With Multiple Instantiations
08:39
Voltage Droop And Ground Bounce
09:12
Power Mesh Solution
07:06
Section 9: Summary
Summary
08:15
Section 10: Quiz and Evaluation
1 question

1 question

Which of the below scenario is correct ?
1 question
Which Scenario impacts the Victim "the least" ?
1 question
Mark Potentially Unsafe Glitches among the below !!
1 question
Identify Potentially Safe Glitches !!
1 question
1 question

Assume DC noise Margin as 0.17 and Noise width as 0ps

What is the Setup Slack between 'A' and 'B' ? (Clock Period 'T' = 70ps)
1 question
What is Hold Slack between 'B' and 'C' ?
1 question

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Instructor Biography

Kunal Ghosh, Educator & VLSI Expertise from IIT Bombay India

Kunal Ghosh, an Engineer by qualification and Educator by interest. It gives me great energy to help students to understand the Concepts of VLSI and Chip Design used in semiconductor Industry and assist them to achieve goals in Professional world. My course are product of simple Principle I follow at work, Keep it Simple and Sweet, All my lectures are full of info-graphical video, where pictures speaks louder then my words.

Now, to be really successful in the field of VLSI and Semiconductors, you need to take the courses in below order:

1) VLSI Academy - Physical design flow

2) VLSI Academy - Clock tree synthesis - Part 1 & 2

3) VLSI Academy - Signal Integrity

4) VLSI Academy - Static timing analysis (Can be taken in between)

5) VLSI Academy - Circuit design and SPICE simulations Part 1 & Part 2 (This is the core of VLSI, so you can take it in beginning or end)

6) VLSI - Essential concepts and detailed interview guide (This course is a glimpse of all above courses, but for details of each topic, you need to take course 1) to 5).)

Connect with me for more guidance !!

Hope you enjoy the session best of luck for future !!

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