VSD - Clock Tree Synthesis - Part 1

VLSI - Building a chip is like building a city!!
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  • Lectures 25
  • Length 4 hours
  • Skill Level All Levels
  • Languages English
  • Includes Lifetime access
    30 day money back guarantee!
    Available on iOS and Android
    Certificate of Completion
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About This Course

Published 1/2014 English

Course Description

Clock Tree Networks are Pillars and Columns of a Chip.

With these series of lectures, we have explored on-site concepts applied in VLSI industry. It is a One-Stop-Shop to understand industrial VLSI circuits.

The videos will develop an analytical approach to tackle technical challenges while building Clock Tree.

What are the requirements?

  • Individuals having Basic Knowledge of Electrical and Electronics

What am I going to get from this course?

  • CTS Quality Checks (Skew, Power, Latency, etc.)
  • H-Tree
  • Quality Check of H-Tree
  • Clock Tree Buffering
  • Buffered H-Tree
  • H-Tree with uneven spread of Flops
  • Advanced H-Tree for Million Flops
  • Power Aware CTS (clock gating)
  • Static Timing Analysis with Clock Tree

Who is the target audience?

  • Individuals keen to learn about VLSI and Chip World

What you get with this course?

Not for you? No problem.
30 day money back guarantee.

Forever yours.
Lifetime access.

Learn on the go.
Desktop, iOS and Android.

Get rewarded.
Certificate of completion.


Introduction to Clock Tree Synthesis
Section 2: Clock Tree Quality Check Parameters
Skew and Pulse Width Check
Duty Cycle and Latency Check
Latency and Power Check
Power Check Continued
Power and Crosstalk Quality Check
Delta Delay Quality Check
Glitch Quality Check
Section 3: H - Tree
H-Tree Algorithm and Skew Check
H-Tree Pulse Width and Duty Cycle Check
H-Tree Latency and Power Check
Section 4: Clock Tree Modelling and Observations
Clock Tree Modelling
Clock Tree Building
Clock Tree Buffering
Clock Tree Observations
Section 5: Buffered H - Tree
H-Tree Buffering Observations
H-Tree Skew Check
H-Tree Pulse Width Check and Issues with Regular Buffers
CMOS Inverter PMOS/NMOS Switching Resistance Difference
CMOS Inverter PMOS/NMOS Matching Switching Resistance Solution
H-Tree with Clock Buffers and Pulse Width Check
H-Tree Duty Cycle, Latency and Power Checks
Dynamic Power and Short Circuit Power
Leakage Power
Section 6: Conclusion
Conclusion and next topics!
Section 7: Interview Questions
1 question

Buffer Levels
1 question
1 question
Clock Gating
1 question
Setup Slack
1 question
Setup Slack - I
1 question
Short Circuit Power
1 question
Delay Table
1 question
Leakage Current
1 question
Total Chip Power
1 question

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Instructor Biography

Kunal Ghosh, Growth Hacker & Co-Founder at VLSI System Design(VSD)

As a 'Growth Hacker', I intend to help students/professionals build their profile even stronger in semiconductors and VLSI, by creating courses at every possible domain in Back end. The experiments which I perform in VSD courses using open-source EDA tools, are of similar complexity of current chip design industry. Till date I have nurtured around 10000+ students and professionals through videos and many of them have been placed or moved to leading semiconductor industries. I have been doing this part time for past 6 years, and now doing this full time at VSD. Happy Learning!!

Now, to be really successful in the field of VLSI and Semiconductors, you need to take the courses in below order:

1) VSD - Physical design flow

2) VSD - Clock tree synthesis - Part 1 & 2

3) VSD - Signal Integrity

4) VSD - Static timing analysis - Part 1 & 2 (Can be taken in between)

5) VSD - Circuit design and SPICE simulations Part 1 & Part 2 (This is the core of VLSI, so you can take it in beginning or end)

6) VLSI - Essential concepts and detailed interview guide (This course is a glimpse of all above courses, but for details of each topic, you need to take course 1) to 5).)

7) VSD - Custom Layout (Can be taken in between)

Connect with me for more guidance !!

Hope you enjoy the session best of luck for future !!

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