VSD - Clock Tree Synthesis - Part 1
4.0 (120 ratings)
Instead of using a simple lifetime average, Udemy calculates a course's star rating by considering a number of different factors such as the number of ratings, the age of ratings, and the likelihood of fraudulent ratings.
948 students enrolled
Wishlisted Wishlist

Please confirm that you want to add VSD - Clock Tree Synthesis - Part 1 to your Wishlist.

Add to Wishlist

VSD - Clock Tree Synthesis - Part 1

VLSI - Building a chip is like building a city!!
4.0 (120 ratings)
Instead of using a simple lifetime average, Udemy calculates a course's star rating by considering a number of different factors such as the number of ratings, the age of ratings, and the likelihood of fraudulent ratings.
948 students enrolled
Created by Kunal Ghosh
Last updated 5/2016
English
Current price: $10 Original price: $95 Discount: 89% off
1 day left at this price!
30-Day Money-Back Guarantee
Includes:
  • 4 hours on-demand video
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
What Will I Learn?
  • CTS Quality Checks (Skew, Power, Latency, etc.)
  • H-Tree
  • Quality Check of H-Tree
  • Clock Tree Buffering
  • Buffered H-Tree
  • H-Tree with uneven spread of Flops
  • Advanced H-Tree for Million Flops
  • Power Aware CTS (clock gating)
  • Static Timing Analysis with Clock Tree
View Curriculum
Requirements
  • Individuals having Basic Knowledge of Electrical and Electronics
Description

Clock Tree Networks are Pillars and Columns of a Chip.

With these series of lectures, we have explored on-site concepts applied in VLSI industry. It is a One-Stop-Shop to understand industrial VLSI circuits.

The videos will develop an analytical approach to tackle technical challenges while building Clock Tree.

Who is the target audience?
  • Individuals keen to learn about VLSI and Chip World
Students Who Viewed This Course Also Viewed
Curriculum For This Course
25 Lectures
03:57:26
+
INTRODUCTION
1 Lecture 10:05
+
Clock Tree Quality Check Parameters
7 Lectures 01:07:23
Skew and Pulse Width Check
10:02

Duty Cycle and Latency Check
10:15

Latency and Power Check
10:20

Power Check Continued
09:54

Power and Crosstalk Quality Check
10:46

Delta Delay Quality Check
08:32

Glitch Quality Check
07:34
+
H - Tree
3 Lectures 29:30
H-Tree Algorithm and Skew Check
09:41

H-Tree Pulse Width and Duty Cycle Check
09:51

H-Tree Latency and Power Check
09:58
+
Clock Tree Modelling and Observations
4 Lectures 39:12
Clock Tree Modelling
09:26

Clock Tree Building
10:21

Clock Tree Buffering
09:58

Clock Tree Observations
09:27
+
Buffered H - Tree
9 Lectures 01:29:52
H-Tree Buffering Observations
11:06

H-Tree Skew Check
10:54

H-Tree Pulse Width Check and Issues with Regular Buffers
09:13

CMOS Inverter PMOS/NMOS Switching Resistance Difference
10:26

CMOS Inverter PMOS/NMOS Matching Switching Resistance Solution
09:51

H-Tree with Clock Buffers and Pulse Width Check
10:48

H-Tree Duty Cycle, Latency and Power Checks
09:28

Dynamic Power and Short Circuit Power
09:46

Leakage Power
08:20
+
Conclusion
1 Lecture 01:24
Conclusion and next topics!
01:24
+
Interview Questions
0 Lectures 00:00

Skew
1 question

Buffer Levels
1 question

Latency
1 question

Clock Gating
1 question

Setup Slack
1 question

Setup Slack - I
1 question

Short Circuit Power
1 question

Delay Table
1 question

Leakage Current
1 question

Total Chip Power
1 question
About the Instructor
Kunal Ghosh
4.3 Average rating
1,440 Reviews
11,600 Students
14 Courses
Digital and Sign-off expert at VLSI System Design(VSD)

I received MTech Degree in Department of Electrical Engineering (EE) from Indian Institute of Technology (IIT) Bombay in 2010 and specialized in VLSI Design & Nanotechnology during my 3-year tenure at IIT Bombay, from 2007 - 2010.

Corporate Life @

1) Lead Physical design and STA engineer, Qualcomm, Bangalore India, 07/2010-04/2013

2) Lead Sales Application engineer, Cadence Design systems, Bangalore India, 04/2013-01/17

Hands on with Technology @

1) MSM (mobile station mode chips) - MSM chips are used for CDMA modulation/demodulation. It consists of DSP’s and microprocessors for running applications such as web-browsing, video conferencing, multimedia services, etc.

2) Memory test chips - Memory test chips are used to validate functionality of 28nm custom/compiler memory as well as characterize their timing, power and yield.

3) DDR-PHY test chips - DDR-PHY test chips are basically tested for high speed data transfer

4) Timing and physical design Flow development for 130nm MOSFET technology node till 16nm FinFET technology node.

5) “IR aware STAandLow power STA

6) Analyzed STA engine behavior for design size up to 850 million instance count

ACADEMIC

1) Research Assistant to Prof. Richard Pinto and Prof. Anil Kottantharayil on “Sub-100nm optimization using Electron Beam Lithography”, which intended to optimize RAITH-150TWO Electron Beam Lithography tool and the process conditions to attain minimum resolution, use the mix-and-match capabilities of the tool for sub-100nm MOSFET fabrication and generate mask plates for feature sizes above 500nm.

2) Research Assistant to with Prof. Madhav Desai, to characterize RTL, generated from C-to-RTL AHIR compiler, in terms of power, performance and area. This was done by passing RTL, generated from AHIR compiler, through standard ASIC tool chain like synthesis and place & route. The resulting netlist out of PNR was characterized using standard software

PUBLICATION 

1) “A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems” submitted in the conference “13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France

2) Concurrent + Distributed MMMC STA for 'N' views

3) Signoff Timing and Leakage Optimization On 18M Instance Count Design With 8000 Clocks and Replicated Modules Using Master Clone Methodology With EDI Cockpit

4) Placement-aware ECO Methodology - No Slacking on Slack

Online Presence - Courses on Udemy

Now, to be really successful in the field of VLSI and Semiconductors, you need to take the courses in below order:

1) VSD - Physical design flow

2) VSD - Clock tree synthesis - Part 1 & 2

3) VSD - Signal Integrity

4) VSD - Static timing analysis - Part 1 & 2 (Can be taken in between)

5) VSD - Circuit design and SPICE simulations Part 1 & Part 2 (This is the core of VLSI, so you can take it in beginning or end)

6) VLSI - Essential concepts and detailed interview guide (This course is a glimpse of all above courses, but for details of each topic, you need to take course 1) to 5).)

7) VSD - Custom Layout (Can be taken in between) 

8) VSD - Library characterization and modelling - Part 1 (STA-1 and 2, Circuit design and SPICE simulations-1 and 2 are mandatory)

Connect with me for more guidance !!

Hope you enjoy the session best of luck for future !!