VSD - Clock Tree Synthesis - Part 2
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VSD - Clock Tree Synthesis - Part 2

VLSI - Building a chip is like building a city!!
Best Seller
3.9 (58 ratings)
Instead of using a simple lifetime average, Udemy calculates a course's star rating by considering a number of different factors such as the number of ratings, the age of ratings, and the likelihood of fraudulent ratings.
486 students enrolled
Created by Kunal Ghosh
Last updated 8/2016
English
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Current price: $10 Original price: $95 Discount: 89% off
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Includes:
  • 4 hours on-demand video
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
What Will I Learn?
  • CTS Quality Checks (Skew, Power, Latency, etc.)
  • H-Tree
  • Quality Check of H-Tree
  • Clock Tree Buffering
  • Buffered H-Tree
  • H-Tree with uneven spread of Flops
  • Advanced H-Tree for Million Flops
  • Power Aware CTS (clock gating)
  • Static Timing Analysis with Clock Tree
View Curriculum
Requirements
  • Individuals having Basic Knowledge of Electrical and Electronics
Description

This course is a follow-up course of "VLSI Academy - Clock tree synthesis - Part 1". So its highly recommended to go through Part 1 of clock tree synthesis

Clock is a critical part of any VLSI chip, and this course takes you to the advanced level of building a clock tree from scratch for millions of flop. 

While we plan to add some experimental videos and courses very soon, as a supplement, this one has real time examples and problems that you see on a real chip, and even solutions to those problems

The course is structured in below format:

1) Introduction

2) Clock tree optimization checklist

3) How to build clock tree for uneven spread of clock end-points

4) Power aware clock tree synthesis

5) Static timing analysis with real clocks

Sounds interesting !! Right !! So get in and have the greatest learning experience like you had never before

See you in class!!

Who is the target audience?
  • Individuals keen to learn about VLSI and Chip World
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Curriculum For This Course
25 Lectures
04:05:34
+
Introduction
1 Lecture 01:26
+
Clock Tree Optimization Checklist
5 Lectures 46:25
Optimization Checklist
09:48


Leakage Current Reduction Technique
10:34

Clock Tree Optimized
09:41

Optimized Clock Tree Power And Latency Check
06:47
+
Uneven Spread of Clock Endpoints
4 Lectures 42:05
Clock Tree for Uneven Spread of Clock End Points
09:55

Logical to Physical Connections
10:11

Checklist
10:47

Advanced H-Tree for Million Flop clock endpoints with uneven spread
11:12
+
Power Aware Clock Tree Synthesis
9 Lectures 01:31:10
Introduction to clock gating cells
09:10

Introduction to Delay Tables
11:12

Delay Table Usage - I
09:21

Delay Table Usage - II
09:30

Clock Gating Technique using AND Gate and Skew Issue
10:29

Solution to Skew Issue
10:03

Clock Gating technique using both AND and OR gate
09:49

Clock Gating Technique using universal NAND gate
10:40

Clock Gating Technique on real Chip and its impact on Power
10:56
+
Static Timing Analysis
5 Lectures 52:02
Setup Timing Analysis with Real Clocks
09:48

Introduction to Data Arrival Time, Data Required Time and Slack
11:12

Impact of unbalanced Skew on Setup Time
10:00

Hold Timing Analysis with Real Clocks
09:43

Impact of unbalanced Skew on Hold Time
11:19
+
Summary
1 Lecture 12:26
Topics Learned and More to come!!
12:26
About the Instructor
Kunal Ghosh
4.3 Average rating
1,736 Reviews
12,704 Students
14 Courses
Digital and Sign-off expert at VLSI System Design(VSD)

I received MTech Degree in Department of Electrical Engineering (EE) from Indian Institute of Technology (IIT) Bombay in 2010 and specialized in VLSI Design & Nanotechnology during my 3-year tenure at IIT Bombay, from 2007 - 2010.

Corporate Life @

1) Lead Physical design and STA engineer, Qualcomm, Bangalore India, 07/2010-04/2013

2) Lead Sales Application engineer, Cadence Design systems, Bangalore India, 04/2013-01/17

Hands on with Technology @

1) MSM (mobile station mode chips) - MSM chips are used for CDMA modulation/demodulation. It consists of DSP’s and microprocessors for running applications such as web-browsing, video conferencing, multimedia services, etc.

2) Memory test chips - Memory test chips are used to validate functionality of 28nm custom/compiler memory as well as characterize their timing, power and yield.

3) DDR-PHY test chips - DDR-PHY test chips are basically tested for high speed data transfer

4) Timing and physical design Flow development for 130nm MOSFET technology node till 16nm FinFET technology node.

5) “IR aware STAandLow power STA

6) Analyzed STA engine behavior for design size up to 850 million instance count

ACADEMIC

1) Research Assistant to Prof. Richard Pinto and Prof. Anil Kottantharayil on “Sub-100nm optimization using Electron Beam Lithography”, which intended to optimize RAITH-150TWO Electron Beam Lithography tool and the process conditions to attain minimum resolution, use the mix-and-match capabilities of the tool for sub-100nm MOSFET fabrication and generate mask plates for feature sizes above 500nm.

2) Research Assistant to with Prof. Madhav Desai, to characterize RTL, generated from C-to-RTL AHIR compiler, in terms of power, performance and area. This was done by passing RTL, generated from AHIR compiler, through standard ASIC tool chain like synthesis and place & route. The resulting netlist out of PNR was characterized using standard software

PUBLICATION 

1) “A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems” submitted in the conference “13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France

2) Concurrent + Distributed MMMC STA for 'N' views

3) Signoff Timing and Leakage Optimization On 18M Instance Count Design With 8000 Clocks and Replicated Modules Using Master Clone Methodology With EDI Cockpit

4) Placement-aware ECO Methodology - No Slacking on Slack

Online Presence - Courses on Udemy

Now, to be really successful in the field of VLSI and Semiconductors, you need to take the courses in below order:

1) VSD - Physical design flow

2) VSD - Clock tree synthesis - Part 1 & 2

3) VSD - Signal Integrity

4) VSD - Static timing analysis - Part 1 & 2 (Can be taken in between)

5) VSD - Circuit design and SPICE simulations Part 1 & Part 2 (This is the core of VLSI, so you can take it in beginning or end)

6) VLSI - Essential concepts and detailed interview guide (This course is a glimpse of all above courses, but for details of each topic, you need to take course 1) to 5).)

7) VSD - Custom Layout (Can be taken in between) 

8) VSD - Library characterization and modelling - Part 1 (STA-1 and 2, Circuit design and SPICE simulations-1 and 2 are mandatory)

Connect with me for more guidance !!

Hope you enjoy the session best of luck for future !!