VSD - Circuit Design & SPICE Simulations - Part 1
4.6 (97 ratings)
Instead of using a simple lifetime average, Udemy calculates a course's star rating by considering a number of different factors such as the number of ratings, the age of ratings, and the likelihood of fraudulent ratings.
681 students enrolled
Wishlisted Wishlist

Please confirm that you want to add VSD - Circuit Design & SPICE Simulations - Part 1 to your Wishlist.

Add to Wishlist

VSD - Circuit Design & SPICE Simulations - Part 1

Learn how things got started in VLSI
Best Seller
4.6 (97 ratings)
Instead of using a simple lifetime average, Udemy calculates a course's star rating by considering a number of different factors such as the number of ratings, the age of ratings, and the likelihood of fraudulent ratings.
681 students enrolled
Created by Kunal Ghosh
Last updated 5/2016
English
Current price: $10 Original price: $95 Discount: 89% off
5 hours left at this price!
30-Day Money-Back Guarantee
Includes:
  • 4 hours on-demand video
  • 5 Articles
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
What Will I Learn?
  • Understand, in brief, Physics of MOSFET
  • Run SPICE simulations on your own and test your own circuits
  • Get better understanding of Timing Analysis
  • Learn VLSI from scratch to advanced (this includes my other courses as well)
View Curriculum
Requirements
  • Basic understanding on Industiral physical design flow, clock tree synthesis and static timing analysis to get applications of this course
  • Even if you are not aware of above one's, that's even better, you can start from scratch
Description

So, you are a professional in VLSI, doing tons of tapeouts and accurate timing analysis.

OR, say, you are a student, who already went through my previous courses on clock tree synthesis, physical design flow and crosstalk,

But, sit back, and give it a thought "Have you done it all?" "Did you know, where does the delay of a cell actually comes from?" "We have learnt about delay models, but are the models accurate?" "How do you verify, if what you are doing in static timing analysis, is correct?" and many more.

These are some of curious questions we wonder about, but hardly find any answers. Even if we found the answers, as a passionate learner, we are still more curious to do some practical things on our own.

And, here's the answer to all of them. SPICE (Simulation Program for Integrated Circuit Emphasis). This course has answers to almost all questions that you might have as a serious timing analyst

So let's get started and keep those questions coming in the forum, and I will answer all of them.

See you in class !!

Who is the target audience?
  • Anyone interested to know, what drives this $Billion VLSI industry
  • Anyone looking to do some practical and hands-on work on SPICE simulations
  • Any professional already doing Static Timing Analysis and wants to go into details of delay models
  • Anyone looking to stay for a long time in VLSI domain
Students Who Viewed This Course Also Viewed
Curriculum For This Course
30 Lectures
03:50:40
+
Introduction to circuit design and SPICE simulations
4 Lectures 37:34

Introduction to basic element in circuit design - NMOS
09:27

Strong inversion and threshold voltage
09:19

Threshold voltage with positive substrate potential
08:18
+
NMOS Resistive region and saturation region of operation
6 Lectures 51:43
Resistive region of operation with small drain-source voltage
09:48


Drain current model for linear region of operation
09:41

SPICE conclusion to resistive operation
04:27

Pinch-off region condition
09:44

Drain current model for saturation region of operation
09:28
+
Introduction to SPICE
6 Lectures 40:46

Circuit description in SPICE syntax
09:14

Define technology parameters
09:24


First SPICE Simulation
10:07

+
SPICE simulation for lower nodes and velocity saturation effect
7 Lectures 38:34
SPICE simulation for lower nodes (250nm)
09:35


Drain current vs gate voltage for long and short channel device
09:49



Velocity variation at lower and higher electric fields
09:09

Velocity saturation drain current model
09:32
+
CMOS voltage transfer characteristics
6 Lectures 59:37
MOSFET as a switch
09:31

Introduction to standard MOS voltage current parameters
10:09

PMOS NMOS drain current v/s drain voltage
10:18

Step1 - Convert PMOS gate-source-voltage to Vin
09:55


Step4 - Merge PMOS - NMOS load curves and plot VTC
10:56
+
Conclusion and next steps
1 Lecture 01:48
+
Quiz
0 Lectures 00:00
Threshold voltage
7 questions
About the Instructor
Kunal Ghosh
4.4 Average rating
1,873 Reviews
13,210 Students
15 Courses
Digital and Sign-off expert at VLSI System Design(VSD)

I received MTech Degree in Department of Electrical Engineering (EE) from Indian Institute of Technology (IIT) Bombay in 2010 and specialized in VLSI Design & Nanotechnology during my 3-year tenure at IIT Bombay, from 2007 - 2010.

Corporate Life @

1) Lead Physical design and STA engineer, Qualcomm, Bangalore India, 07/2010-04/2013

2) Lead Sales Application engineer, Cadence Design systems, Bangalore India, 04/2013-01/17

Hands on with Technology @

1) MSM (mobile station mode chips) - MSM chips are used for CDMA modulation/demodulation. It consists of DSP’s and microprocessors for running applications such as web-browsing, video conferencing, multimedia services, etc.

2) Memory test chips - Memory test chips are used to validate functionality of 28nm custom/compiler memory as well as characterize their timing, power and yield.

3) DDR-PHY test chips - DDR-PHY test chips are basically tested for high speed data transfer

4) Timing and physical design Flow development for 130nm MOSFET technology node till 16nm FinFET technology node.

5) “IR aware STAandLow power STA

6) Analyzed STA engine behavior for design size up to 850 million instance count

ACADEMIC

1) Research Assistant to Prof. Richard Pinto and Prof. Anil Kottantharayil on “Sub-100nm optimization using Electron Beam Lithography”, which intended to optimize RAITH-150TWO Electron Beam Lithography tool and the process conditions to attain minimum resolution, use the mix-and-match capabilities of the tool for sub-100nm MOSFET fabrication and generate mask plates for feature sizes above 500nm.

2) Research Assistant to with Prof. Madhav Desai, to characterize RTL, generated from C-to-RTL AHIR compiler, in terms of power, performance and area. This was done by passing RTL, generated from AHIR compiler, through standard ASIC tool chain like synthesis and place & route. The resulting netlist out of PNR was characterized using standard software

PUBLICATION 

1) “A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems” submitted in the conference “13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France

2) Concurrent + Distributed MMMC STA for 'N' views

3) Signoff Timing and Leakage Optimization On 18M Instance Count Design With 8000 Clocks and Replicated Modules Using Master Clone Methodology With EDI Cockpit

4) Placement-aware ECO Methodology - No Slacking on Slack

Online Presence - Courses on Udemy

Now, to be really successful in the field of VLSI and Semiconductors, you need to take the courses in below order:

1) VSD - Physical design flow

2) VSD - Clock tree synthesis - Part 1 & 2

3) VSD - Signal Integrity

4) VSD - Static timing analysis - Part 1 & 2 (Can be taken in between)

5) VSD - Circuit design and SPICE simulations Part 1 & Part 2 (This is the core of VLSI, so you can take it in beginning or end)

6) VLSI - Essential concepts and detailed interview guide (This course is a glimpse of all above courses, but for details of each topic, you need to take course 1) to 5).)

7) VSD - Custom Layout (Can be taken in between) 

8) VSD - Library characterization and modelling - Part 1 (STA-1 and 2, Circuit design and SPICE simulations-1 and 2 are mandatory)

Connect with me for more guidance !!

Hope you enjoy the session best of luck for future !!