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So, you are a professional in VLSI, doing tons of tapeouts and accurate timing analysis.
OR, say, you are a student, who already went through my previous courses on clock tree synthesis, physical design flow and crosstalk,
But, sit back, and give it a thought "Have you done it all?" "Did you know, where does the delay of a cell actually comes from?" "We have learnt about delay models, but are the models accurate?" "How do you verify, if what you are doing in static timing analysis, is correct?" and many more.
These are some of curious questions we wonder about, but hardly find any answers. Even if we found the answers, as a passionate learner, we are still more curious to do some practical things on our own.
And, here's the answer to all of them. SPICE (Simulation Program for Integrated Circuit Emphasis). This course has answers to almost all questions that you might have as a serious timing analyst
So let's get started and keep those questions coming in the forum, and I will answer all of them.
See you in class !!
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|Section 1: Introduction to circuit design and SPICE simulations|
Why do we need circuit design and SPICE simulations?Preview
Introduction to basic element in circuit design - NMOS
Strong inversion and threshold voltage
Threshold voltage with positive substrate potential
|Section 2: NMOS Resistive region and saturation region of operation|
Resistive region of operation with small drain-source voltage
Drift current theoryPreview
Drain current model for linear region of operation
SPICE conclusion to resistive operation
Pinch-off region condition
Drain current model for saturation region of operation
|Section 3: Introduction to SPICE|
Basic SPICE setupPreview
Circuit description in SPICE syntax
Define technology parameters
Standard technology filePreview
First SPICE Simulation
SPICE deck for 1.2u Technology nodePreview
|Section 4: SPICE simulation for lower nodes and velocity saturation effect|
SPICE simulation for lower nodes (250nm)
SPICE deck for 250nm Technology nodePreview
Drain current vs gate voltage for long and short channel device
Id-Vgs SPICE deck for 1.2u technology nodePreview
Id-Vgs SPICE deck for 250nm technology nodePreview
Velocity variation at lower and higher electric fields
Velocity saturation drain current model
|Section 5: CMOS voltage transfer characteristics|
MOSFET as a switch
Introduction to standard MOS voltage current parameters
PMOS NMOS drain current v/s drain voltage
Step1 - Convert PMOS gate-source-voltage to Vin
Step2 & Step3 - Convert PMOS and NMOS drain-source-voltage to voutPreview
Step4 - Merge PMOS - NMOS load curves and plot VTC
|Section 6: Conclusion and next steps|
Conclusion and next stepsPreview
|Section 7: Quiz|
As a 'Growth Hacker', I intend to help students/professionals build their profile even stronger in semiconductors and VLSI, by creating courses at every possible domain in Back end. The experiments which I perform in VSD courses using open-source EDA tools, are of similar complexity of current chip design industry. Till date I have nurtured around 10000+ students and professionals through videos and many of them have been placed or moved to leading semiconductor industries. I have been doing this part time for past 6 years, and now doing this full time at VSD. Happy Learning!!
Now, to be really successful in the field of VLSI and Semiconductors, you need to take the courses in below order:
1) VSD - Physical design flow
2) VSD - Clock tree synthesis - Part 1 & 2
3) VSD - Signal Integrity
4) VSD - Static timing analysis - Part 1 & 2 (Can be taken in between)
5) VSD - Circuit design and SPICE simulations Part 1 & Part 2 (This is the core of VLSI, so you can take it in beginning or end)
6) VLSI - Essential concepts and detailed interview guide (This course is a glimpse of all above courses, but for details of each topic, you need to take course 1) to 5).)
7) VSD - Custom Layout (Can be taken in between)
Connect with me for more guidance !!
Hope you enjoy the session best of luck for future !!