VSD - Circuit Design & SPICE Simulations - Part 2
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VSD - Circuit Design & SPICE Simulations - Part 2

Learn how things got started in VLSI
4.9 (24 ratings)
Instead of using a simple lifetime average, Udemy calculates a course's star rating by considering a number of different factors such as the number of ratings, the age of ratings, and the likelihood of fraudulent ratings.
354 students enrolled
Created by Kunal Ghosh
Last updated 2/2017
English
Current price: $10 Original price: $95 Discount: 89% off
5 hours left at this price!
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Includes:
  • 3 hours on-demand video
  • 7 Articles
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
What Will I Learn?
  • Understand, in brief, Physics of MOSFET
  • Run smart SPICE simulations on your own and test your own circuits
  • Get better understanding of Timing Analysis
  • Learn VLSI from scratch to advanced (this includes my other courses as well)
View Curriculum
Requirements
  • Basic understanding on Industiral physical design flow, clock tree synthesis and static timing analysis to get applications of this course
  • Even if you are not aware of above one's, that's even better, you can start from scratch
Description

This is a follow-up course on my previous one "Circuit design and SPICE simulations - Part1" 

It is a must, that you go through Part 1 of this course, to fully understand and apply using open source tools. This course will help you do some advanced quick SPICE simulations, while you analyze the behavior of your devices.

In this course we will cover:

1.Voltage Transfer Characteristics - SPICE simulations

2.Static behavior Evaluation : CMOS inverter Robustness

•Switching Threshold

•Noise margin

•Power supply variation

•Device variation

So let's get started (again) and keep those questions coming in the forum, and I will answer all of them.

See you in class !!


Who is the target audience?
  • Anyone interested to know, what drives this $Billion VLSI industry
  • Anyone looking to do some practical and hands-on work on SPICE simulations
  • Any professional already doing Static Timing Analysis and wants to go into details of delay models
  • Anyone looking to stay for a long time in VLSI domain
Compare to Other Circuit Design Courses
Curriculum For This Course
26 Lectures
02:53:59
+
Introduction
1 Lecture 00:58
+
Voltage Transfer Characteristics - SPICE simulations
5 Lectures 23:24
+
Static behavior Evaluation : CMOS inverter Robustness - Switching Threshold
6 Lectures 01:00:08
Switching Threshold, Vm
09:33

Analytical expresssion of Vm as a function of (W/L)p and (W/L)n
11:02

Analytical expression of (W/L/)p and (W/L)n as a function of Vm
09:30


Static and dynamic simulation of CMOS inverter with increased PMOS width
10:05

Applications of CMOS inverter in clock network and STA
09:48

Switching threshold quiz
6 questions
+
Static behavior Evaluation : CMOS inverter Robustness - Noise Margin
4 Lectures 36:56
Introduction to noise margin
09:08

Noise margin voltage parameters
08:56

Noise margin equation and summary
08:25

Noise margin variation with respect to PMOS width
10:27

Noise margin quiz
4 questions
+
Static behavior Evaluation : CMOS inverter Robustness - Power supply variation
4 Lectures 23:36
Smart SPICE simulation for power supply variations
10:01



Advantages and disadvantages using low supply voltage
10:49

Power supply variation quiz
4 questions
+
Static behavior Evaluation : CMOS inverter Robustness - Device variation
5 Lectures 24:56
Sources of variation - Etching process
09:43

Sources of variation - oxide thickness
04:42

Smart SPICE simulation for device variations
07:39



Device variation quiz
2 questions
+
Conclusion
1 Lecture 06:35
Conclusion
06:35
About the Instructor
Kunal Ghosh
4.4 Average rating
1,895 Reviews
13,244 Students
15 Courses
Digital and Sign-off expert at VLSI System Design(VSD)

I received MTech Degree in Department of Electrical Engineering (EE) from Indian Institute of Technology (IIT) Bombay in 2010 and specialized in VLSI Design & Nanotechnology during my 3-year tenure at IIT Bombay, from 2007 - 2010.

Corporate Life @

1) Lead Physical design and STA engineer, Qualcomm, Bangalore India, 07/2010-04/2013

2) Lead Sales Application engineer, Cadence Design systems, Bangalore India, 04/2013-01/17

Hands on with Technology @

1) MSM (mobile station mode chips) - MSM chips are used for CDMA modulation/demodulation. It consists of DSP’s and microprocessors for running applications such as web-browsing, video conferencing, multimedia services, etc.

2) Memory test chips - Memory test chips are used to validate functionality of 28nm custom/compiler memory as well as characterize their timing, power and yield.

3) DDR-PHY test chips - DDR-PHY test chips are basically tested for high speed data transfer

4) Timing and physical design Flow development for 130nm MOSFET technology node till 16nm FinFET technology node.

5) “IR aware STAandLow power STA

6) Analyzed STA engine behavior for design size up to 850 million instance count

ACADEMIC

1) Research Assistant to Prof. Richard Pinto and Prof. Anil Kottantharayil on “Sub-100nm optimization using Electron Beam Lithography”, which intended to optimize RAITH-150TWO Electron Beam Lithography tool and the process conditions to attain minimum resolution, use the mix-and-match capabilities of the tool for sub-100nm MOSFET fabrication and generate mask plates for feature sizes above 500nm.

2) Research Assistant to with Prof. Madhav Desai, to characterize RTL, generated from C-to-RTL AHIR compiler, in terms of power, performance and area. This was done by passing RTL, generated from AHIR compiler, through standard ASIC tool chain like synthesis and place & route. The resulting netlist out of PNR was characterized using standard software

PUBLICATION 

1) “A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems” submitted in the conference “13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France

2) Concurrent + Distributed MMMC STA for 'N' views

3) Signoff Timing and Leakage Optimization On 18M Instance Count Design With 8000 Clocks and Replicated Modules Using Master Clone Methodology With EDI Cockpit

4) Placement-aware ECO Methodology - No Slacking on Slack

Online Presence - Courses on Udemy

Now, to be really successful in the field of VLSI and Semiconductors, you need to take the courses in below order:

1) VSD - Physical design flow

2) VSD - Clock tree synthesis - Part 1 & 2

3) VSD - Signal Integrity

4) VSD - Static timing analysis - Part 1 & 2 (Can be taken in between)

5) VSD - Circuit design and SPICE simulations Part 1 & Part 2 (This is the core of VLSI, so you can take it in beginning or end)

6) VLSI - Essential concepts and detailed interview guide (This course is a glimpse of all above courses, but for details of each topic, you need to take course 1) to 5).)

7) VSD - Custom Layout (Can be taken in between) 

8) VSD - Library characterization and modelling - Part 1 (STA-1 and 2, Circuit design and SPICE simulations-1 and 2 are mandatory)

Connect with me for more guidance !!

Hope you enjoy the session best of luck for future !!