VSDOpen2020 - VLSI online conference

This lecture presents applying community models to IC design, showing how a global open source community can empower designers, remove upfront costs, and provide IP, reference designs, and services.

Explore how global creator communities power open collaboration, open innovation, and open source to accelerate semiconductor design, product development, and IoT through crowdsourced ideas and design challenges.

Open source IP and open PDK models lower costs and accelerate IC design by removing collaboration barriers, with examples from Google, SkyWater, and Air Force challenges.

Explore how open source hardware and community-driven design accelerate ICs development with raven and RISC-V case studies. See how education, industry, and security benefit from transparent collaboration and open models.

Discover an eight-week IP design internship program that engaged about five thousand students in open source hardware, culminating in 22 successful completions and community-driven silicon IP projects.

Design a 32 kbits SRAM at 1.8 v with <2.5 ns access, detailing block diagrams, input and control signals, and data storage considerations for open technologies.

Explore next-gen open-source VLSI and RISC-V trainings on VSD-IAT and Makerchip, featuring automated, self-paced labs on a global platform for accessible microarchitecture education.

Explore next-gen open-source VLSI and RISC-V training through VSD-IAT and Makerchip, featuring a five-stage RISC-V pipeline built with open tools and ABI integration.

Explore upcoming VLSI workshops at the VSDOpen2020 conference, featuring microprocessor design and advanced physical design using cloud-based open line Skyland, with student-focused labs.

Open source hardware creates a unique opportunity for India to build a semiconductor industry. Leverage IoT, 5G, and edge computing to design secure, low-margin, region-specific edge chips at scale.

Explore how open innovation enables domain-specific, edge-ready chips designed for fast deployment under a year, integrating hardware and software with open standards for security, and a customer-centric, India-focused approach.

Explore building hardware startups quickly with a customer-centric fastpass approach to hardware development, leveraging core IP, security IP, and software tools, tapping India's opportunities across IoT, fintech, AI, and defense.

Explore a 10-bit potentiometric dac design redesigned in an open-source workflow using 180 nm technology, highlighting hierarchical layout, capacitor-based switching networks, and simulation-driven verification.

Analyze the 10-bit potentiometric DAC performance, plotting analog output versus input codes and assessing non-linearity, gain error, and offset error, with simulation-supported results across the code range.

Explore on-chip clock multiplication using a phase-locked loop to convert 5–12.5 mhz input into 40–100 mhz output, via a voltage-controlled oscillator, feedback divider, and an additional divider for eightfold multiplication.

Explains the physical design of an on-chip clock multiplier PLL, including the PFG, voltage control oscillator, frequency dividers and detectors, and layout considerations for power, performance, and area.

This lecture demonstrates an on-chip pll clock multiplier achieving eight to ten times input frequency, from 5–12.5 mhz to 40–100 mhz, noting Sky 130 Bidegain and GitHub collaboration for work.

Explore how post-moore era challenges demand open source collaboration to redefine system design, as ai and web services outpace traditional scaling.

Explore how 3d memory, packaging strategies, and reconfigurable interconnects enable dense storage and networks, while evaluating multiple roadmaps for CMOS architectures, memory, and accelerators.

Reframe system architecture across all abstraction layers with complete architectural models and open hardware and software, enabling 3D integration, memory architectures, and energy-efficient AI accelerators.

Open source enables distributed intelligence across devices in the post-moore era, expanding memory, compute, and wireless communication as core design considerations for cloud and edge computing.

Trace the brief history of open source software and learn how its licensing, four freedoms, and hacker culture illuminate open hardware principles for today.

Explain the open source definition and four freedoms, contrast free software with open source, and show how licensing and a cathedral versus bazaar approach shape derived works and source-code access.

Explain copyleft licenses and the contrast between GPL and permissive licenses, and trace open source software and hardware from RISC architectures to open source silicon and European policy.

Explore open hardware and free software licenses, including permissive and copyleft variants, and learn how copyright law shapes hardware designs, open hardware practices, and community-driven innovation.

Collaborate on the 10-bit ADC design as a student team develops an ABC IP, converting analog inputs to digital outputs through iterative logic and highlighting high-precision applications.

Explore the 10-bit ADC design, focusing on the sample-and-hold function, its low-power high-speed benefits, and the comparator’s role in producing a digital output. Examine challenges like non-monotonicity and linearity across code transitions, and discuss design trade-offs referenced from historical 80s surveys and open-source approaches.

The lecture describes the 10-bit ADC part 3, detailing the flip-flop based block that compares the sampled input to a reference, iterates through cycles, and outputs the final value.