VSDOpen2019 - VLSI online conference

Open source epa accelerates research and education by enabling an open rtl2gds flow and 24/7 hardware compilers through the Open Road project, delivering drc-clean rtl to gds layouts.

Explore open source EDA for RTL to GDS using an incremental shared net list architecture, timer API, and a collaborative open road workflow.

Open source eda and rtl2gds implementation drive collaboration in the open road project, showcasing machine learning for icd design, ongoing tutorials in Bangalore, and opportunities to contribute.

Explore the Raven chip’s first silicon success with qflow and efabless in an open source IC design ecosystem, plus a live silicon demo on the development board.

Demonstrates Raven chip silicon success with qflow efabless, detailing architecture components, a web-based FCC configuration flow, PPA and cost modeling, and firmware programming on a Raven development board.

Watch the Raven chip demo configuring the ADC inputs from external sources, clocks, and a 10-bit ADC, streaming values over serial and driving an LCD bar from ADC readings.

Unleash open source silicon by overcoming implementation detail, tool access, and hardware access barriers, and leverage cloud fpga for hardware acceleration of open silicon.

Open source silicon accelerates industry-wide collaboration by up leveling behavior with higher level modeling and safe register transfer level details, enabling easy IP sharing and cloud FPGA workflows.

Demonstrates using cloud resources and the Xilinx tool stack to debug, measure timing, and optimize hardware kernels, then run bitstreams on FPGA via F1 instances and hardware emulation.

Explore how cloud-integrated environments and local open-source simulation simplify hardware development on FPGA, lowering costs and enabling open-source silicon to reshape the industry.

Explore the growing momentum and opportunity of the RISC-V open architecture, highlighting open source initiatives, strategic partnerships, and industry collaboration shaping open hardware ecosystems.

Explore the growing momentum and opportunities of the RISC-V open architecture, including open instruction sets, user-mode versus supervisory designs, and the role of the RISC-V Foundation in advancing openness.

Boom is a high-performance, open-source 64-bit RISC-V out-of-order core implemented in chisel RTL. As a parameterizable generator, it integrates with the rocketship ecosystem and can run Linux unmodified.

Explore the boom out-of-order core as a configurable research platform for attaching accelerators, studying spectre mitigations, and using shipyard, chisel, fertile, fire-sim, and hammer to design open-source risk five systems.

Explore rocket ship, the Berkeley out-of-order machine baseline, a versatile SSP generator with order cores and STC components, and its silicon-proven tapeout and FireSim FPGA workflow.

Discover Chips Alliance, an open source hardware ecosystem that develops open IP, interconnect IP, tools, and standards under governance, with Apache-style licensing and global membership for collaborative projects.

Chips alliance promotes open source hardware by sharing IP blocks and verification flows, enabling risk five cores and linux-capable designs with an RTL simulator, Python tooling, and cloud-based verification.

This invited talk introduces CHIPS Alliance and open source hardware collaboration, highlighting design verification workshops, open source tools, and international events to lower hardware development costs.

Explore the fabless transformation of the semiconductor industry, from IDM to fabless with foundries, Moore's law as observation, and the evolving design enablement, IP ecosystem, and the foundry landscape.

Gain startup-focused insights into fabless semiconductor transformation, emphasizing analog design, exits, and digital demand creation through webinars, blogging, and a cloud-based ecosystem.

Explore the PULP project, an energy-efficient open-source hardware initiative delivering A6 cores, RISC-V cores, peripherals, and scalable platforms under an Apache-like license.

Explore the PULP project in 15 minutes, part 2, showcasing open hardware cores and peripherals, industry adoption, and collaborations with open hardware groups and universities.

Discover how embedded UVM enables multicore testbenches using an open source hardware workflow, with designs mapped to an FPGA on a Cortex-A9 platform and cloud-based CI for open verification.

Embedded UVM enables multicore testbenches with a portable, system programming–enabled environment that implements 1.0 standard with reg package and constrained randomization, integrating RTL simulations and FPGA accelerators.