VSDOpen2018 - First ever online VLSI conference
- 5.5 hours on-demand video
- Full lifetime access
- Access on mobile and TV
- Certificate of Completion
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- Access to 6 symposia to cover all aspects of semiconductor technology with prime focus to build SoC using RISC-V CPU by illustrating exciting ways in the field of RTL design with Transaction-Level Verilog, Library characterization, Clock tree synthesis, Floorplanning, Placement & Routing, and Machine intelligence all using Opensource EDA tool
- Experience first online conference in VLSI and semiconductor industry
- Current presence in VLSI industry is needed
- Should be open to observe current trends happening in the field of RISC-V and open-source EDA
VSDOpen2018, the six hours program, responds to many trends and challenges in semiconductor design using open source hardware tools and developing the IP to reach the silicon level, with papers and presentation in the research paper sessions covering the core set of design topics: Front-end open-source EDA tool flows for IC design and verification, Clock tree synthesis and optimization of digital IC’s for best Performance, Floorplanning of digital IC’s for best area, Place and Route of digital IC’s for best PPA, Standard cell layout/characterization for compact area/high performance/minimal routing resources, Machine Learning in EDA.
Key highlights of this conference were:
Keynote by Prof. David Patterson on "A New Golden Age in Computer Architecture"
Keynote by Prof. Sharon Hu on "Professional growth with ACM SIGDA"
Keynote by Mohamed Kaseem on "Applying open community innovation to hardware product creation"
Apart from above keynotes, here are some interesting papers, on RISC-V and opensource EDA which were presented
TAU 2019 contest announcement by George Chen from Intel
Padframe generator for qflow (an opensource RTL2GDS tool) by Phillip Guhring, Vienna Austria
PNR of digital core IC using cloud based EDA tool by Anand Rajgopalan, Mumbai University
Coverage driven functional verification on RISC-V cores, by Lavanya J., Anmol Sahoo, Paul George from IIT Madras
Rapid Physical IC implementation and integration using efabless platform by Alberto Gomez Saiz, Imperial college, London
Introduction to TL-Verilog by Steve Hoover, Redwood EDA
Formally verifying WARP-V, an open-source TL-Verilog RISC-V Core generator by Akos Hadnagy, TU Delft
Top-down transaction level design with TL-Verilog by Ahmed Salman, Alexandria University
- Beginner with knowledge on Application oriented SoC using RISC-V as CPU, cloud FPGA
- Anyone with knowledge on Clock tree strategy for complex RISC-V CPU to achieve best performance in terms of skew and pulse width
- Anyone with knowledge on Floorplanning for RISC-V CPU like picoRV32/E31_coreplex_IP to achieve best area
- Anyone with knowledge on PNR strategy for complex blocks/full chip to achieve best PPA and runtime
- Anyone with knowledge on Layout/Characterization of standard cells/IP’s using Magic/Guna