Udemy
    •  
    •  
    •  
    •  
    •  
    •  
    •  
    •  
Subscribe
Turn what you know into an opportunity and reach millions around the world.
Learn More
Your cart is empty.
Keep shopping
VSDOpen2018 - First ever online VLSI conference
Rating: 4.0 out of 5(45 ratings)
3,052 students

VSDOpen2018 - First ever online VLSI conference

Conducted LIVE online on 27th October, 2018
Created byKunal Ghosh
Last updated 4/2019
English

What you'll learn

  • Semiconductor technology and design developed in Open source environment
  • Access to 6 symposia to cover all aspects of semiconductor technology with prime focus to build SoC using RISC-V CPU
  • Experience first online conference in VLSI and semiconductor industry
  • Illustration of exciting ways to build your CPU using all opensource EDA tools

Course content

13 sections • 35 lectures • 5h 28m total length

  • Introduction to VSDOpen conference, keynote speakers and paper presenters12:32

    discover the first online vsdopen conference, featuring keynote speakers and paper presenters, with discussions on open source ideas and next-generation chip design.

Requirements

  • Current presence in VLSI industry is needed
  • Should be open to observe current trends happening in the field of RISC-V and open-source EDA

Description

VSDOpen2018, the six hours program, responds to many trends and challenges in semiconductor design using open source hardware tools and developing the IP to reach the silicon level, with papers and presentation in the research paper sessions covering the core set of design topics: Front-end open-source EDA tool flows for IC design and verification, Clock tree synthesis and optimization of digital IC’s for best Performance, Floorplanning of digital IC’s for best area, Place and Route of digital IC’s for best PPA, Standard cell layout/characterization for compact area/high performance/minimal routing resources, Machine Learning in EDA.

Key highlights of this conference were:

  1. Keynote by Prof. David Patterson on "A New Golden Age in Computer Architecture"

  2. Keynote by Prof. Sharon Hu on "Professional growth with ACM SIGDA"

  3. Keynote by Mohamed Kaseem on "Applying open community innovation to hardware product creation"

Apart from above keynotes, here are some interesting papers, on RISC-V and opensource EDA which were presented

  1. TAU 2019 contest announcement by George Chen from Intel

  2. Padframe generator for qflow (an opensource RTL2GDS tool) by Phillip Guhring, Vienna Austria

  3. PNR of digital core IC using cloud based EDA tool by Anand Rajgopalan, Mumbai University

  4. Coverage driven functional verification on RISC-V cores, by Lavanya J., Anmol Sahoo, Paul George from IIT Madras

  5. Rapid Physical IC implementation and integration using efabless platform by Alberto Gomez Saiz, Imperial college, London

  6. Introduction to TL-Verilog by Steve Hoover, Redwood EDA

  7. Formally verifying WARP-V, an open-source TL-Verilog RISC-V Core generator by Akos Hadnagy, TU Delft

  8. Top-down transaction level design with TL-Verilog by Ahmed Salman, Alexandria University

Who this course is for:

  • Beginner with knowledge on Application oriented SoC using RISC-V as CPU, cloud FPGA
  • Anyone with knowledge on Clock tree strategy for complex RISC-V CPU to achieve best performance in terms of skew and pulse width
  • Anyone with knowledge on Floorplanning for RISC-V CPU like picoRV32/E31_coreplex_IP to achieve best area
  • Anyone with knowledge on PNR strategy for complex blocks/full chip to achieve best PPA and runtime
  • Anyone with knowledge on Layout/Characterization of standard cells/IP’s using Magic/Guna

Report abuse