VSDOpen2018 - First ever online VLSI conference
What you'll learn
- Semiconductor technology and design developed in Open source environment
- Access to 6 symposia to cover all aspects of semiconductor technology with prime focus to build SoC using RISC-V CPU by illustrating exciting ways in the field of RTL design with Transaction-Level Verilog, Library characterization, Clock tree synthesis, Floorplanning, Placement & Routing, and Machine intelligence all using Opensource EDA tool
- Experience first online conference in VLSI and semiconductor industry
Requirements
- Current presence in VLSI industry is needed
- Should be open to observe current trends happening in the field of RISC-V and open-source EDA
Description
VSDOpen2018, the six hours program, responds to many trends and challenges in semiconductor design using open source hardware tools and developing the IP to reach the silicon level, with papers and presentation in the research paper sessions covering the core set of design topics: Front-end open-source EDA tool flows for IC design and verification, Clock tree synthesis and optimization of digital IC’s for best Performance, Floorplanning of digital IC’s for best area, Place and Route of digital IC’s for best PPA, Standard cell layout/characterization for compact area/high performance/minimal routing resources, Machine Learning in EDA.
Key highlights of this conference were:
Keynote by Prof. David Patterson on "A New Golden Age in Computer Architecture"
Keynote by Prof. Sharon Hu on "Professional growth with ACM SIGDA"
Keynote by Mohamed Kaseem on "Applying open community innovation to hardware product creation"
Apart from above keynotes, here are some interesting papers, on RISC-V and opensource EDA which were presented
TAU 2019 contest announcement by George Chen from Intel
Padframe generator for qflow (an opensource RTL2GDS tool) by Phillip Guhring, Vienna Austria
PNR of digital core IC using cloud based EDA tool by Anand Rajgopalan, Mumbai University
Coverage driven functional verification on RISC-V cores, by Lavanya J., Anmol Sahoo, Paul George from IIT Madras
Rapid Physical IC implementation and integration using efabless platform by Alberto Gomez Saiz, Imperial college, London
Introduction to TL-Verilog by Steve Hoover, Redwood EDA
Formally verifying WARP-V, an open-source TL-Verilog RISC-V Core generator by Akos Hadnagy, TU Delft
Top-down transaction level design with TL-Verilog by Ahmed Salman, Alexandria University
Who this course is for:
- Beginner with knowledge on Application oriented SoC using RISC-V as CPU, cloud FPGA
- Anyone with knowledge on Clock tree strategy for complex RISC-V CPU to achieve best performance in terms of skew and pulse width
- Anyone with knowledge on Floorplanning for RISC-V CPU like picoRV32/E31_coreplex_IP to achieve best area
- Anyone with knowledge on PNR strategy for complex blocks/full chip to achieve best PPA and runtime
- Anyone with knowledge on Layout/Characterization of standard cells/IP’s using Magic/Guna
Course content
- Preview12:32
Instructor
![Kunal Ghosh](data:image/svg+xml,%3Csvg xmlns="http://www.w3.org/2000/svg" viewBox="0 0 64 64"%3E%3C/svg%3E){kind=avatar}
- 4.3 Instructor Rating
- 10,036 Reviews
- 36,240 Students
- 42 Courses
Kunal Ghosh is the Director and co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd. Prior to launching VSD in 2017, Kunal held several technical leadership positions at Qualcomm's Test-chip business unit. He joined Qualcomm in 2010. He led the Physical design and STA flow development of 28nm, 16nm test-chips. At 2013, he joined Cadence as Lead Sales Application engineer for Tempus STA tool. Kunal holds a Masters degree in Electrical Engineering from Indian Institute of Technology (IIT), Bombay, India and specialized in VLSI Design & Nanotechnology.
Hands on with Technology @
1) MSM (mobile station mode chips) - MSM chips are used for CDMA modulation/demodulation. It consists of DSP’s and microprocessors for running applications such as web-browsing, video conferencing, multimedia services, etc.
2) Memory test chips - Memory test chips are used to validate functionality of 28nm custom/compiler memory as well as characterize their timing, power and yield.
3) DDR-PHY test chips - DDR-PHY test chips are basically tested for high speed data transfer
4) Timing and physical design Flow development for 130nm MOSFET technology node till 16nm FinFET technology node.
5) “IR aware STA” and “Low power STA”
6) Analyzed STA engine behavior for design size up to 850 million instance count ACADEMIC
1) Research Assistant to Prof. Richard Pinto and Prof. Anil Kottantharayil on “Sub-100nm optimization using Electron Beam Lithography”, which intended to optimize RAITH-150TWO Electron Beam Lithography tool and the process conditions to attain minimum resolution, use the mix-and-match capabilities of the tool for sub-100nm MOSFET fabrication and generate mask plates for feature sizes above 500nm.
2) Research Assistant to with Prof. Madhav Desai, to characterize RTL, generated from C-to-RTL AHIR compiler, in terms of power, performance and area. This was done by passing RTL, generated from AHIR compiler, through standard ASIC tool chain like synthesis and place & route. The resulting netlist out of PNR was characterized using standard software
PUBLICATION
1) “A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems” submitted in the conference “13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France”
2) Concurrent + Distributed MMMC STA for 'N' views
3) Signoff Timing and Leakage Optimization On 18M Instance Count Design With 8000 Clocks and Replicated Modules Using Master Clone Methodology With EDI Cockpit
4) Placement-aware ECO Methodology - No Slacking on Slack
Tips on order in which you need to learn VLSI and become a CHAMPION:
If I would had been you, I would had started with Physical Design and Physical design webinar course where I understand the entire flow first, then would have moved to CTS-1 and CTS-2 to look into details of how the clock is been built.
Then, as you all know how crosstalk impacts functioning at lower nodes, I would gone for Signal Integrity course to understand impacts of scaling and fix them. Once I do that, I would want to know how to analyze performance of my design and I would have gone for STA-1, STA-2 and Timing ECO webinar courses, respectively
Once you STA, there’s an internal curiosity which rises, and wants us to understand, what goes inside timing analysis at transistor level. To full-fill that, I would had taken Circuit design and SPICE simulations Part 1 and Part 2 courses.
And finally, to understand pre-placed cells, IP’s and STA in even more detail, I would have taken custom layout course and Library Characterization course
All of above needs to be implemented using a CAD tool and needs to be done faster, for which I would have written TCL or perl scripts. So for that, I would start to learn TCL-Part1 and TCL-Part2 courses, at very beginning or in middle
Finally, if I want to learn RTL and synthesis, from specifications to layout, RISC-V ISA course will teach the best way to define specs for a complex system like microprocessor
Connect with me for more guidance !!
Hope you enjoy the session best of luck for future