VSD - TCL programming - From novice to expert - Part 2

Explore a simple one-bit memory rtl with two addresses, data in/out, and a clocked write/read cycle, and how the bios tool generates a gate-level netlist.

Explore memory functionality and synthesis using Yosys by analyzing address decoding, undefined values, and data flow on clock edges, and by converting Verilog memory models to gate-level netlists.

Explore memory read operation and TCL scripting agenda, detailing how clocked read, select lines, and memory outputs work, and how to automate TCL scripts from Verilog netlists for design flows.

Master TCL scripting to perform a hierarchy check on Verilog netlists, reading library data, loading and dumping design data to files, and validating the top-to-bottom hierarchy.

Learn how to generate a hierarchy check script in TCL by parsing Verilog netlists, globbing directories, and capturing data into files with put and open operations.

Explore error handling in a hierarchy check script, showing how to detect missing models, report indices from the log, and use pattern matching with normalization to debug bios design issues.

Explore a demo for an error handling script that performs hierarchy checks, uses 0/1 flags and if-then-else logic, saves modifications, and generates user-facing logs and messages about models and architectures.

Learn to create a synthesis script, generate and dump it into a file, run ABC logic based synthesis on RDL, and interpret log files and errors during a live demo.

Edit the yosys output netlist by filtering out unwanted star lines, removing backslashes, and saving a clean output file using grep, vi, and shell redirection.

Explore editing the output netlist using a virtual box, and learn how to define and use procs in TCL, including arguments and example blocks.

Demonstrate how to redirect stdout in TCL using a proc and the array command, with practical demos showing how options map to values and how usage blocks parse arguments.

Explore how the set_multi_cpu_usage proc demonstrates TCL argument handling, including dollar expansions, hyphen semantics, and globbing, and how a switch directs multiple options and their optional values.

Explore the set_multi_cpu_usage proc through a demo, running a standalone block, examining options and arguments, printing outputs, and displaying the usage message.

Learn to read an sdc file, remove square brackets, and replace them with a null character, preparing data for downstream processing in Tcl programming.

Explore parsing a processed SDC to evaluate clock period and identify grid clocks, clock stops, and clock port names, then generate clocks with a script using TCL basics.

Explore how to evaluate duty cycle and define clock timing in opentimer format, mapping clock period to rising edges and percentage values with practical examples.

Learn to grep clock latency and port names from SDC files using TCL, applying pattern matching, list operations, and dummy port handling to extract timing data efficiently.

Convert set_clock_latency from SDC to opentimer format by mapping clock delays across four list elements, validating indices and values to produce accurate latency representations.

The lecture demonstrates scripting to convert transition and input delay into the opentimer format, mapping global constraints, timing data, and delay constraints with live demos.

Convert output sdc constraints to opentimer format, modeling the output interface through a scripting workflow that handles constraints, decoding scripts, and bus expansion to individual bits.

Create an OpenTimer configuration file to pass design netlists and library parts for static timing analysis. Generate timing reports, check for negative slack, and extend scripts to append necessary lines.

Learn to write a Tcl script to extract runtime (sta runtime) from a design, measure time in microseconds, convert to seconds, and output formatted reports to a results file.