VSD - Pipelining RISC-V with Transaction-Level Verilog

Learn how to describe a pipelined RISC-V block diagram using transaction-level Verilog, covering combinational and sequential logic, pipeline interactions, and hardware verification on the Maker Chip platform.

Describe how a RISC-V pipeline fetches instructions through fetch, decode, register read, execute, and register write stages, and how hazards like branches and load-use are detected and mitigated with forwarding.

Examine out-of-order execution and superscalar designs in a wider RISC-V pipeline, balancing hazard detection with memory bottlenecks and unrolling dependencies via pending registers and replay.

Explore challenges of building a flexible RISC-V IP for diverse CPUs, and demonstrate a parameterized transaction-level Verilog model (Work5) enabling configurable pipeline depth and ISA, with high-level synthesis trends.

Discover transactional Verilog, a transaction-level hardware language built atop SystemVerilog that treats hardware as parallel, with abstraction guiding detail, enabling explicit, flexible design for pipelines.

Learn how makerchip.com enables transaction-level Verilog design, bypassing many traditional Verilog complexities, and explore the platform's editor, compile-sim-debug workflow with waveforms, diagrams, and tutorials.

Learn the makerchip workflow for transaction-level Verilog: edit in the browser, compile in the cloud with Sandpiper, generate Verilog and logs, and complete the first participant exercise by loading tutorials.

Explore a Verilog inverter exercise on makerchip, compile and simulate, and learn how to save projects, view waveforms, and handle common editor issues and warnings.

Learn transaction-level verilog alongside system verilog testbench concepts, control simulation with past and fail signals, and implement sequential fibonacci logic using flip-flops and reset in a pipelined risc-v context.

Join a live Q&A on transaction-level Verilog, covering a counter and Fibonacci-style pipeline logic, with ahead-by-1 and ahead-by-2 operations, reset behavior, and indentation rules.

Explore how a pipeline splits processing into stages and uses a Pythagoras theorem example to illustrate computing distance with transactional level Verilog and pipe signals across cycles.

Explore retiming in a timing-abstract design using TL-Verilog and compare with SystemVerilog, focusing on clock domains, staging, and safe timing modifications.

Revisit fibonacci as a pipeline with explicit fetch, decode, and execute stages; show parameterizable staging, hazards, and a validity signal for clearer, correct transaction-level verilog modeling.

learn clock gating to reduce power in high-frequency circuits and apply an exercise to detect instruction errors in warp-v using or-gate logic for illegal addresses, misalignment, and overflow.

Explore how the WARP-V operand mux handles immediate values, bypassed results, and memory data in a pipelined RISC-V design. Learn about relative timing, staging adjustments, and safe RTL level changes.

Explore register file bypass and two-stage, time-aware muxing to avoid hazards in a RISC-V pipeline, then model the lab to slice packets into flits and reassemble them every fourth cycle.

Demonstrate a time-division multiplexing exercise by implementing reset handling and a valid pulse every fourth cycle from a template, using chained ternaries to pack the count into a 3-bit payload.

Solve TDM exercise part 2 demonstrates pipelining RISC-V with Transaction-Level Verilog by forming the packet from four components, grabbing lower bits first, and aligning bits to output a valid packet.

Engage in a live Q&A on verification workflows, using template code and raw system Verilog display to validate packets, discuss MakerChip limits, UVM absence, and certification challenge.

Explore how Verilog and TL-Verilog manage hierarchy and interfaces—from module hierarchies and arrays to replication and generate loops, illustrated by Conway's Game of Life.

Explore the emergence of transaction-level Verilog for the WARP-V core, including a silicon-proven FPGA design, openness to community contributions, and guidance on Sandpiper tool flows.

Define your module and interface in Verilog, then implement the guts in transaction level Verilog using timing abstract pipe signals and explore transaction flow through pipelines and rings.

Design a transaction-level Verilog circuit for a certification challenge that iteratively computes a distance using Pythagoras, starting from 16 and updating every two cycles.

Deliver warm thanks to participants and Steve, announce upcoming part two on transaction-level Verilog and future ideas, and invite engagement via email or social sharing.