VSD - Pipelining RISC-V with Transaction-Level Verilog
4.3 (44 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
362 students enrolled

VSD - Pipelining RISC-V with Transaction-Level Verilog

Front end VLSI design can’t get easier than this
4.3 (44 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
362 students enrolled
Last updated 2/2018
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Current price: $61.99 Original price: $94.99 Discount: 35% off
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This course includes
  • 3.5 hours on-demand video
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
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What you'll learn
  • Students will be able to use and implement concepts of pipelining using TL-verilog language and Makerchip platform
  • Build their own verilog models for IP's using a simpler and powerful Verilog design environment
Requirements
  • You should know basics of digital design like flip-flops, gates, clock, etc.
  • You should have finished RISC-V ISA - Part 1a course on Udemy if new to CPU microarchitecture
  • You should have a modern web browser like chrome, and login to Makerchip to ensure compatibility
Description

Do you want to build just verilog models or high-quality verilog models in half the time? 

Have you implemented a processor using Verilog? Which was the most important part of your implementation? What was your code size in Verilog? What if, we told you that you can reduce your verilog code size by about 3.5x by a new technology? What if, we told you that you can create any digital sequential logic you can dream up faster than you ever thought possible, all within your browser?

How about a ‘change’? Change the way you used to write your verilog code. Change the way you used to implement Pipelining for your processor. Change is the only “constant”. I encourage and welcome you to think in the right direction with experts from this field in my webinar on “Pipelining RISC-V with Transaction-Level Verilog” which was conducted on 10th Feb’ 2018 with Steve Hoover, Founder of Redwood EDA and Makerchip Platform

This webinar is really important for people who have taken up my RISC-V ISA course on Udemy, as we will show efficient RTL implementation of some instructions in this one.

Enjoy the webinar and Happy Learning....

Who this course is for:
  • Anyone who wants to learn transaction-level verilog
  • Anyone who wants to stay ahead of curve in frontend VLSI
  • Anyone who wants to learn and implement pipelining concepts in field of computer architecture
Course content
Expand all 27 lectures 03:38:06
+ Introduction
3 lectures 20:47
Launch of makerchip.com and introduction to webinar motive
10:15
Live QnA with participants on webinar content and motive
07:03
+ RISC-V overview and instruction Pipelining Concepts
3 lectures 22:51
RISC-V waterfall diagram and hazards
06:09
Live QnA with participants regarding processor architecture
08:31
+ IP design methodology
3 lectures 26:01
RISC-V IP challenges and WARP-V development progress
09:12
Why Transaction-Level verilog?
07:27
Introduction to makerchip.com platform
09:22
+ Examples using makerchip.com platform
4 lectures 40:44
More about makerchip.com and first exercise for participants
10:15
Inverter exercise for participants and LIVE QnA about makerchip.com platform
08:48
LIVE QnA with participants regarding exercises
11:52
+ Pipelines
4 lectures 36:07
Pythagoras theorem example of pipeline
07:47
Retiming implementation in TL-Verilog vs system verilog
10:10
Exercise to identify error conditions in WARP-V
08:10
+ Pipeline Interactions
5 lectures 36:36
WARP-V operand mux
08:56
Register bypass and time division multiplexing (TDM) example
08:47
Solve TDM exercise - Part1
08:10
Solve TDM exercise - Part2
06:05
LIVE QnA with participants regarding pipeline interactions and other topics
04:38
+ Miscellaneous Topics
3 lectures 21:53
Hierarchy and interfaces in TL-Verilog
07:10
LIVE QnA with participants on WARP-V core
04:22
Transaction flow and wrap-up course content
10:21