VSD - Physical Design Webinar using EDA tool 'Proton'

Explore open source physical design flows using Proton, from logic synthesis to floor planning and placements, with open tooling, zero license fees, and webchip.in as the design collaboration platform.

Launch the Proton EDA tool live on the web, log in with Google, and run bench experiments across Chrome and Internet Explorer while troubleshooting setup.

Describe the multiplier functionality, including how multiplicand and multiplier are handled in binary and decimal and how 64-bit inputs yield 128-bit products in two consecutive memory locations, with open-source verification.

Verify the 16 by 16 bit RTM design in Proton using iverilog, leveraging open-source RTL from GitHub to validate clocked inputs, signals, and verification benches.

Import and explore physical libraries and standard cells, inspect timing and physical libraries, and view lef to understand cell sizing and timing considerations in Proton.

Engage in a live Q&A on using the Proton EDA tool for LEF workflows, covering dot files, netlists, data restrictions, and NDA considerations for physical design.

Navigate the synthesis workflow from binding logic to physical cells, import design files, generate a netlist, and elaborate the design data for physical mapping in qflow yosys.

Join a live QnA on synthesis algorithm for Proton-driven physical design. Explore mapping, constraints, timing analysis, and library integration with participant discussions.

Master pre-layout timing analysis with the Proton EDA tool, calculating maximum delays and frequency from clock to flip-flop to output, complemented by a live QnA.

Explore floorplanning concepts driven by netlists, defining utilization factor and aspect ratio, and visualize block areas. Learn power planning with grids and power rings to supply standard cells.

A practical guide to locating power and ground rails in standard cells and macros, tapping from power rings, and routing grids with Proton.

Explore power planning strategies for proton physical design, including sourcing power from the nearest location to minimize drop, managing blockages and constraints, and discussing floorplan views and capsule integration.

Explore cell and automated pin placement concepts in Proton via Graywolf, starting from floor planning to normal placement and IO file-driven auto placement, with optimization across partitions.

Explore live q&a on cell and pin placement using Proton, balancing local and global density, padding, and soft grouping to minimize blockages and improve data flow.

Analyze placement and clock tree synthesis in Proton, and demo flylines, showcasing how buffers, clock nets, and decoupling capacitors manage RC delay and timing.

Explore live q&a on flylines and demo routing in Proton, showing placement strategy, shortest-path maze approaches, timing-driven net weighting, and the design browser for instance names and design options.

Learn to run commands to analyze and report routing statistics in Proton, perform timing analysis with extraction, and verify design rules and spacing through DRC checks.

Explore post-layout timing analysis steps using Proton, generate timing reports, measure timing, and discuss enabling new features with command options and open formats for enhanced design insight.

Explore timing eco strategies in physical design with proton, balancing condition based and timing based design to optimize insertion delay, setup, and hold across nets.

Explore assignment details and upcoming webinars for the proton-based physical design, and learn power analysis, large power grid design, and verification within open-source licensing contexts.

Plan future enhancements for the Proton physical design tool, improving timing checks and clock-to-flop reporting, and addressing power, licensing, and open-source access.

Wraps up a Ben and Rajiv interactive discussion, invites feedback via the feedback form, shares contact details, and commits to improving platform access for a successful, collaborative webinar.