VSD - Mixed-signal RISC-V based SoC on FPGA

Name: VSD - Mixed-signal RISC-V based SoC on FPGA
Rating: 3.7 (8 reviews)

FPGA flow for Mixed Signal SoC with RISC-V based core and PLL IP

Created byKunal Ghosh, Shivani Shah

Last updated 7/2021

English

English [Auto],

What you'll learn

FPGA flow vs ASIC flow
Basic mixed-signal RISC-V based SoC RTL design and simulations
FPGA Synthesis, bit-stream generation and simulation

Course content

4 sections • 14 lectures • 1h 16m total length

Introduction2:03
Integrate digital and analog IP on a single chip using a PLL clock multiplier and a test program with instruction memory, validated by Ivory logging and the Xilinx toolchain.

RVMYTH RISC-V Core2:45
Explore a five-stage pipeline RVMYTH RISC-V core in Verilog. Trace the fetch, decode, execute, memory address calculation, and write-back path for a load.
Transaction level Verilog4:49
Master transaction level verilog, a transaction level modeling approach that reduces code size, clarifies pipelining and retiming, and enables a highly parametrized five-core SoC on FPGA.
Why FPGAs ?1:25
Explain why fpgas are needed today, highlighting their reconfigurability for rapid prototyping and verification in mixed-signal design, and the nearly one-year design time for a complex design.
Makerchip platform7:17
Demonstrates the makerchip platform for converting hardware descriptions into visual diagrams, writing modular code, and compiling with simulated inputs, while navigating tutorials and project workflows.
TL - Verilog to RTL verilog5:16
Learn how Verilog to RTL conversion is performed using the Sandpiper code generator, with repository setup, installation, and top-level module instantiation for a functional model.
Functional Simulation using iverilog9:17
Explore functional simulation with iverilog by driving an instruction sequence, initializing memory, executing add and loop instructions, and verifying digital-to-analog signals via a PLL and FPGA output.

FPGA - Steps to create project8:25
Configure a pll ip with an input clock to yield the required frequency, then create the project, select the board, and generate ip for simulation and fpga flow.
FPGA - Steps to generate IPs8:06
Explore instantiating and configuring FPGA IP cores, including clocking with PLLs, enabling internal signals, and choosing options. Verify with an integrative logic analyzer and prepare the IP for generation.
FPGA - RTL simulation9:24
Explore FPGA RTL simulation of a mixed-signal RISC-V based SoC, verifying functionality by running timed simulations, adjusting clocks, and comparing digital and analog outputs with markers and asserts.
FPGA - Synthesis5:17
Explore FPGA synthesis for a mixed-signal RISC-V-based SoC on FPGA, covering constraints, clock creation, simulation, implementation, timing analysis, and resolving slack and timing violations.
FPGA - Implementation and timing analysis5:31
Explain FPGA implementation and timing analysis, including PLL instantiation and handling clock violations. Apply constraints to ignore false paths and perform synthesis and implementation checks.
FPGA - Bit-stream generation, FPGA programming and ILA4:13

Requirements

VSD - RISC-V ISA course on Udemy
VSD - Pipelining RISC-V using TL-Verilog course on Udemy

Description

This webinar helps you get started with a basic mixed-signal FPGA flow, which can be extended to any complex SoC.

VSD and RedwoodEDA conducts 5-day RISC-V based MYTH (Microprocessors for You in Thirty Hours) workshop using transaction level Verilog on Makerchip platform. For people who have done this workshop can use this webinar as an extension to the 5th Day, where RISC-V pipe-lined CPU coded in TL-Verilog is now converted to verilog language and is a part of a mixed-signal SoC

If you are from ASIC/Physical design back-ground, this webinar will complement your existing work, and you would really get to know similarities and differences between ASIC and FPGA flow, which one is preferred under what conditions and why is it preferred

This single webinar connects VLSI students, analog designers, FPGA designers and ASIC designers. It is also an attempt to bring everyone on the same platform, and serves as a starting point for design verification

Stay tuned for follow-up series of FPGA webinars and 5-day hands-on high intensity FPGA workshop, which will be built around OpenFPGA framework and Makerchip visualization software, that enables the whole community to learn FPGA fundamentals along with labs, without actually having a physical FPGA board.

Innovation at its best

All the best and happy learning

Who this course is for:

Beginner in FPGA design
Beginner in VLSI design
Experienced Physical Design and STA engineers

VSD - Mixed-signal RISC-V based SoC on FPGA

What you'll learn

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Course content

Introduction1 lecture • 2min

Mixed Signal SoC details with RISC-V core and PLL IP6 lectures • 31min

Mixed Signal FPGA flow6 lectures • 41min

Conclusion1 lecture • 2min

Requirements

Description

Who this course is for: