VSD - Making the Raven chip: How to design a RISC-V SoC
4.3 (74 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
539 students enrolled

VSD - Making the Raven chip: How to design a RISC-V SoC

Building a chip is like building a city....
4.3 (74 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
539 students enrolled
Last updated 3/2018
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Current price: $65.99 Original price: $94.99 Discount: 31% off
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This course includes
  • 4.5 hours on-demand video
  • Full lifetime access
  • Access on mobile and TV
  • Assignments
  • Certificate of Completion
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What you'll learn
  • Students will be able to build and configure their own SoC (System-On Chip)
  • Students will be able to create their own defition of GPIO
  • Understand decision making process like, analog peripheral (ADC, DAC, POR, etc.), digital peripheral (UART, flash controller), memory mapping, top level connections like pad-frame, level-shifters, GPIO and many more
Requirements
  • A Linkedin login ID
  • Knowledge on RISC-V is nice to have, but not must to have
  • Digital design concepts and a bit of verilog syntax is nice to have
Description

Building a chip is like building a city...

This was the mantra with which we started our company in 2011. Now that we have covered major components of chip designing through our online courses, I think this is the right time to move from "chip designing" to "chip planning"

Chip Planning involves lot of decision making like, analog peripheral (ADC, DAC, POR, etc.), digital peripheral (UART, flash controller), memory mapping, top level connections like pad-frame, level-shifters, GPIO and many more.

Do you want to know what it is like to build a city? Did you know there is no standard definition for GPIOs? Thats the whole point of designing an SOC. Figuring out what things you are going to control outside of the CPU and memory mapping them.

If you look at any microcontroller e.g. PIC microcontroller, the only way to know how you access their ADC or their UART is to go look at their documentation and find out wheres the memory map address for this

Do you want to know how to build and configure your own System-on-Chip (SoC)? Do you want to write your own data sheet?

I welcome you to my webinar which was conducted on Mar 10, 2018. Enroll with myself, Tim Edwards and Mohamed Kassem, and rise above, by being a Core SoC designer and build your own datasheet.

This is the perfect webinar for to grow and stay ahead of curve in Semiconductor and Chip design. Stay tuned and happy learning....

All the best, and I will see you in webinar..

Who this course is for:
  • Anyone who wants to learn SoC planning
  • Anyone who wants to learn chip design from specifications to Layout
  • Anyone curious to know, what happens before Synthesis, Physical design and STA
Course content
Expand all 30 lectures 04:18:15
+ Introduction
3 lectures 20:05
Where does this webinar fits in chip design flow?
07:25
RISC-V basic introduction
06:09
+ efabless platform overview
3 lectures 28:49
efabless model for IP design and login steps to efabless platform
09:26
Introductory interactive tutorial of efabless platform
09:33
+ Steps to characterize analog circuits
3 lectures 24:42
Step to push IP for eg. level shifter to your opengalaxy account
08:44
LIVE QnA with participants regarding efabless platform
08:51
+ Starting the RISC-V SoC Reference Design
4 lectures 31:01
Pre-requisites and RISC-V, picorv32 and picoSoC overview
08:39
Raven SoC and Raven full chip overview
07:50
LIVE QnA regarding Raven full chip design
05:48
Clone Raven chip into opengalaxy environment
08:44
+ Understanding the RISC-V SoC Reference Design
4 lectures 37:10
Interactive tutorial file system and introduction to digital picorv32 core
09:36
SRAM, analog peripherals, real valued verilog and pad-frame
08:41
Voltage domain and LIVE QnA with participants regarding SoC reference design
09:11
+ Design choices
4 lectures 29:03
Design goals and analog components
07:33
LIVE QnA with participants regarding design goals and components
05:35
Memory map
06:24
+ Assembling the parts into a verilog top-level module
4 lectures 40:16
SoC complete memory map and top level connections
10:15
Analog configuration, control memory map, pads and C-code testbench
10:20
C-code testbench and verilog testbench detailed explanation
09:45
Interactive tutorial to run full Raven testbench suite
09:56
+ Making a new testbench
3 lectures 22:15
Interactive tutorial to setup and make a new testbench
08:34
Running and debugging testbench using GTKWave
07:59
LIVE testbench debugging and re-configuring
05:42
Modify the raven_soc verilog to include a timer module Timer is instantiated in the SoC but the module should be in a separate file like the UART is in "simpleuart.v". Call this module "counter_timer.v".
Modify the raven_soc verilog to include a timer module
1 question
+ Assignment and Conclusion
2 lectures 14:48
Detailed assignment description and mode of submission
10:06
Conclusion
04:42