VSD - Machine Intelligence in EDA/CAD
What you'll learn
- Intro to Machine Learning in EDA/CAD
- Develop machine learning apps with TensorfFow and Python in cloud
- Develop EDA and CAD applications like resistance estimation, capacitance estimation, cell classification etc.
- Categories of Machine Learning
- Machine Learning Framework which will cover Python primer and introduction to Tensor flow
- Applied theory, regression and classification
Course content
- Preview10:24
- 09:41Agenda, myths and latest applications of machine intelligence (MI)
Requirements
- Be familiar to basic VLSI chip design flow
- Be familiar with standard nomenclature of VLSI and chip design
- Basic knowledge on Python and Tesnsor Flow is nice to have, but will be anyways covered in the course
Description
This webinar was conducted on 31st March 2018 with Rohit, CEO Paripath Inc.
We start with Electronic design automation and what is machine learning. Then we will give overall introduction to categories of machine learning (supervised and unsupervised learning) and go about discussing that a little bit. Then we talk about the frameworks which are available today, like general purpose, big data processing and deep-learning, and which one is suitable for design automation. This is Machine Learning in general with a focus on CAD, EDA and VLSI flows.
Then we talk about Applied Theory (data sets, data analysis like data augmentation, exploratory data analysis, normalization, randomization), as to what are the terms and terminologies and what do we do with that, accuracy, how do we develop the algorithm, essentially the things that are required to develop the solution flow, lets say, you as the company wants to add a feature in your product using machine learning, what you would be doing, and what your flow will look like and this is what is shown as pre-cursor of flight theory as what you should be looking out.
And then we start with regression, which is first in supervised learning. In the regression, we will give couple of example, like first is resistance estimation, second is polynomial regression which is capacitance estimation. For resistance estimation, we have the dataset from 20nm technology. And finally, we go on to create a linear classifier using logistic regression.
Next will be dimensionality reduction, meaning, you have a large dataset and how to you reduce the size of that so that you can run on a laptop or even on your cell phone. Then there is a big example of that. Everything has mathematics behind that, this wont be a part of the webinar.
About Rohit - Rohit Sharma is Founder and CEO of Paripath Inc based in Milpitas, CA. He graduated from IIT Delhi.He has authored 2 books and published several papers in international conferences and journals. He has contributed to electronic design automation domain for over 20 years learning, improvising and designing solutions. He is passionate about many technical topics including Machine Learning, Analysis, Characterization and Modeling, which led him to architect guna - an advanced characterization software for modern nodes.He currently works for Paripath Inc.
Who this course is for:
- Design automation engineers
- CAD developers
- Managers and executives
- Research professionals and graduate students
- Machine learning enthusiasts and Investors
Instructors
Kunal Ghosh is the Director and co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd. Prior to launching VSD in 2017, Kunal held several technical leadership positions at Qualcomm's Test-chip business unit. He joined Qualcomm in 2010. He led the Physical design and STA flow development of 28nm, 16nm test-chips. At 2013, he joined Cadence as Lead Sales Application engineer for Tempus STA tool. Kunal holds a Masters degree in Electrical Engineering from Indian Institute of Technology (IIT), Bombay, India and specialized in VLSI Design & Nanotechnology.
Hands on with Technology @
1) MSM (mobile station mode chips) - MSM chips are used for CDMA modulation/demodulation. It consists of DSP’s and microprocessors for running applications such as web-browsing, video conferencing, multimedia services, etc.
2) Memory test chips - Memory test chips are used to validate functionality of 28nm custom/compiler memory as well as characterize their timing, power and yield.
3) DDR-PHY test chips - DDR-PHY test chips are basically tested for high speed data transfer
4) Timing and physical design Flow development for 130nm MOSFET technology node till 16nm FinFET technology node.
5) “IR aware STA” and “Low power STA”
6) Analyzed STA engine behavior for design size up to 850 million instance count
ACADEMIC
1) Research Assistant to Prof. Richard Pinto and Prof. Anil Kottantharayil on “Sub-100nm optimization using Electron Beam Lithography”, which intended to optimize RAITH-150TWO Electron Beam Lithography tool and the process conditions to attain minimum resolution, use the mix-and-match capabilities of the tool for sub-100nm MOSFET fabrication and generate mask plates for feature sizes above 500nm.
2) Research Assistant to with Prof. Madhav Desai, to characterize RTL, generated from C-to-RTL AHIR compiler, in terms of power, performance and area. This was done by passing RTL, generated from AHIR compiler, through standard ASIC tool chain like synthesis and place & route. The resulting netlist out of PNR was characterized using standard software
PUBLICATION
1) “A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems” submitted in the conference “13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France”
2) Concurrent + Distributed MMMC STA for 'N' views
3) Signoff Timing and Leakage Optimization On 18M Instance Count Design With 8000 Clocks and Replicated Modules Using Master Clone Methodology With EDI Cockpit
4) Placement-aware ECO Methodology - No Slacking on Slack
Tips on order in which you need to learn VLSI and become a CHAMPION:
If I would had been you, I would had started with Physical Design and Physical design webinar course where I understand the entire flow first, then would have moved to CTS-1 and CTS-2 to look into details of how the clock is been built.
Then, as you all know how crosstalk impacts functioning at lower nodes, I would gone for Signal Integrity course to understand impacts of scaling and fix them. Once I do that, I would want to know how to analyze performance of my design and I would have gone for STA-1, STA-2 and Timing ECO webinar courses, respectively
Once you STA, there’s an internal curiosity which rises, and wants us to understand, what goes inside timing analysis at transistor level. To full-fill that, I would had taken Circuit design and SPICE simulations Part 1 and Part 2 courses.
And finally, to understand pre-placed cells, IP’s and STA in even more detail, I would have taken custom layout course and Library Characterization course
All of above needs to be implemented using a CAD tool and needs to be done faster, for which I would have written TCL or perl scripts. So for that, I would start to learn TCL-Part1 and TCL-Part2 courses, at very beginning or in middle
Finally, if I want to learn RTL and synthesis, from specifications to layout, RISC-V ISA course will teach the best way to define specs for a complex system like microprocessor
Connect with me for more guidance !!
Hope you enjoy the session best of luck for future !!
Rohit Sharma is an engineer, author and entrepreneur. He has published over 10 papers in international conferences and journals. He has contributed to electronic design automation domain for over 20 years learning, improvising and designing solutions. He is passionate about many technical topics including machine learning, analysis, characterization, and modeling. It led him to architect guna - an advanced characterization software for modern nodes. He currently works for Paripath Inc. (paripath.c0m) - a company he founded.