VSD Intern - OpenRAM configuration for 4kB SRAM using Sky130

Name: VSD Intern - OpenRAM configuration for 4kB SRAM using Sky130
Rating: 3.8 (23 reviews)

How to configure ope-source compiler OpenRAM for 130nm technology node

Created byKunal Ghosh, Shon Taware

Last updated 4/2021

English

English [Auto],

What you'll learn

Configure open-source memory compiler OpenRAM for any memory size
SRAM custom cell design
Memory GDS/Lib/Lef file types

Course content

6 sections • 16 lectures • 1h 13m total length

Introduction to OpenRAM2:03
OpenRAM is a Python-based open source memory compiler that configures 4kB sram for sky130 by integrating technology files, constraint scripts, and cell libraries to generate layout, timing, and other models.
Reasons to use OpenRAM and Sky130 technology3:08
OpenRAM and Sky130 enable open-source ram design by using a compiler to arrange replicated memory cells, align ground rules, and respect interconnect and spacing constraints.

OpenRAM environment setup3:57
Configure the OpenRAM environment by installing dependencies, verifying python 3.8.5, and cloning the repository. Set and source environment variables in the Linux VM running on Windows via VirtualBox.
Bit-cells and sense amplifier details5:53
Explore bit-cells and sense amplifier details, including layout and space files for custom cells, differential amplification, and simulations of read/write operations in the OpenRAM 4kB SRAM design.
Dummy & replica bit cells, D-flipflop and write driver details3:52
Examine dummy and replica bit cells for regularity, analyze a D-flipflop built from transmission gates and inverters, and review write driver circuits and sense amplifier timing.

OpenRAM directory structure5:33
Explore the OpenRAM directory structure, study the models directory with spice models for various components, and review the technology files and configurations for Pandora used in Sky130 based 4kB sram.
GDS file creation5:37
Copy the sky130 technology files into the OpenRAM tech directory, then use Magic to load the layout and convert it into a GDS file for 4kB SRAM.
Tech file setup5:52
Create and configure a tech file and map file for OpenRAM, organizing layers, diffusion and top layers, and importing Python libraries to set properties and maps.
Interconnect stack layer name and technology parameters4:01
Demonstrate the interconnect stack architecture, including layer naming, contacts between local interconnect, metal, and vias, back-end-of-line stacks, power grid mapping, and technology parameters such as minimum transistor size.
DRC rules and SPICE technology setup6:30
Configure DRC rules and SPICE technology setup for OpenRAM 4kB SRAM using Sky130; set minimum transistor width, contact spacing, metal and contact overlaps, and SPICE parameters.

OpenRAM configuration script3:51
Configure OpenRAM for a Sky130-based 4kB SRAM by creating a Skyland A config file, setting size and memory depth, selecting execution technology, and running the script in the terminal.
Execute and review OpenRAM output files5:15
Execute and review OpenRAM output files by examining compiler timings, logs, and configuration details. Explore the space model and generated reports to understand ports, timing, and power characteristics.

Custom cells boundry box4:10
Set up the OpenRAM environment for a 4kB SRAM, build a 2x2 cell with at least 16 words, resolve boundary box issues, and convert scripts to layout for success.
GDS pins and tech layers5:41
Master OpenRAM configuration for 4kB sram on Sky130 by diagnosing compiler errors, editing tech layers and gds pins, and validating scripts and rules throughout the design flow.
GDS DRC issues6:35
Address GDS DRC issues by resolving overlapping structures and adjusting tap spacing, running updated scripts, and verifying aligned memory cells and sense amplifiers to ensure a clean layout.

Requirements

VSD - Custom Layout course on Udemy
VSD - Circuit design and SPICE simulation course on Udemy
VSD - Library characterization course on Udemy

Description

This webinar aims at design of 1024x32 SRAM cell array (32Kbits or 4KB) with a configuration of 1.8 V operating voltage and access time less than 2.5ns using Google SkyWater SKY130 PDKs and OpenRAM memory compiler.

Static Random-Access Memory (SRAM) has become a standard element of any Application Specific Integrated Circuit (ASIC), System-On-Chip (SoC), or other micro-architectures. For this wide variety of applications, SRAMs are configured using parameters like the word-length, bit lines, operating voltage, access time, and most importantly the technology node. The access time of an SRAM cell is the time require for a read or write operation of SRAM.

Manually configuring the SRAM for every change in parameter seems a slightly in-efficient and tedious task. Due to this reason, the memory compiler is used on a large scale, as it facilitates easy configuration and optimization of memory. OpenRAM, an open-source memory compiler is used for characterization and generation of SRAM designs.

This webinar mentioned multiple open-source circuit schematic design, layout design, SPICE simulations tools and memory compiler. The tools used are explained in detail. All the Skywater SKY130 PDKs related files are added to the repository mentioned in webinar, which can be used without installing the complete PDKs. To install or get other details of Skywater PDKs, it can be found in Skywater official website

Who this course is for:

VLSI Beginner who wants to quickly learn about various custom cells like 6T-SRAM, DFF
VLSI professionals who want to know how to configure open-source memory compiler OpenRAM for custom memory IP generation

VSD Intern - OpenRAM configuration for 4kB SRAM using Sky130

What you'll learn

Explore related topics

Course content

Introduction2 lectures • 5min

Environment Setup and custom cells description3 lectures • 14min

OpenRAM technology setup5 lectures • 28min

Steps to execute OpenRAM2 lectures • 9min

Challenges, issues and fixes3 lectures • 16min

Conclusion1 lecture • 2min

Requirements

Description

Who this course is for: