VSD Intern - DAC IP Design using Sky130 PDKs - Part 2

Demonstrate the basic principle of potential division with a switch network to generate differential voltages, showing how digital codes produce distinct output potentials as the number of bits increases.

Hierarchical design builds higher-bit structures by replicating unit modules and using switches, simplifying debugging and schematic capture while enabling precise component selection.

Assess two switch options, weighing their advantages and disadvantages across high and low input ranges. Analyze cutoff behavior, transmission grid concepts, and control voltage to select a robust solution.

Calculate resistance by analyzing input parameters, settling time, aspect ratio, and trade-offs with parasitic effects, while balancing mobility and transistor sizing in the transmission grid using inverters and transmission gates.

Learn how to design a switch schematic in Xschem using Sky130 pdk symbols, place instances, edit properties, and include libraries and model definitions for reliable schematic prototyping.

Create and save symbol for reuse, select mixed symbol option, copy and modify switch model, adjust properties, connect next circuit including ground connection, and finalize schematic.

Complete the Xschem switch by building the schematic for the switch, creating a symbol, preparing the netlist, and setting up the corresponding stimulus and comments.

Examine the Xschem 2bit schematic within the VSD Intern DAC IP design using Sky130 PDKs, detailing the design plans, resistors, inputs and outputs, and switch outputs.

Demonstrate building a 10-bit DAC schematic in Xschem by creating reusable symbols, wiring increasing numbers of digital inputs through resistors and switches, and validating the final output.

Use Ngspice to simulate the dac design, organize netlists and subcircuits, apply all digital input combinations, and analyze transient responses with staircase output plots.

Explore ngspice results, plot simulation data, export to MATLAB formats, and interpret voltage values to validate DAC IP designs.

Evaluate the simulator results to verify DEC functionality, analyze design-stack metrics, and review how input combinations affect transient waveforms and spike reduction through connected cuts.

Explain differential nonlinearity and integral nonlinearity as key metrics for nonlinearity, how to calculate them, and how deviations from the ideal output line reveal missing intermediate steps.

In this conclusion, the speaker reviews tool installation, design according to specifications, schematic capture, and verification by simulation, then previews the upcoming layout portfolio automation and termination discussions.