VSD Intern - Analog Comparator Design using Sky130
What you'll learn
- Basics of Analog comparator Circuit design and layout
- Integrate Sky130 foundry PDKs with comparator circuit design
- Basics of comparator hysteresis characteristics
- VSD - Circuit design and SPICE simulations
- VSD - Custom layout
- VSD Intern - Analog Bandgap Reference design using Sky130
A comparator is a device that compares two analog inputs and outputs a digital signal indicating which input is larger. So it has two analog input terminals and one binary digital output. When the difference between two analog input signals approach zero, noise on the inputs will cause spurious switching of digital output. This rapid change in output due to noise can be prevented by hysteresis. Hysteresis is switching the output high or low at different input signal levels. In place of one switching point, hysteresis introduces two: one for rising edge, and one for falling edge of voltage or current. The difference between the higher-level trip value (VH) and the lower-level trip value (VL) equals the hysteresis voltage (HYST).
A comparator can be divided into three distinctive pieces – a front-end differential amplifier, amplifier stage and output stage.
This comparator consists of
Front-end differential amplifier
Amplifier of the output from front-end differential sage
NAND gate to act as buffer as well as incorporate the enable pin
Inverter to act as final buffer before output. The NAND and Inverter improves the slew and provides a little gain.
Positive feedback differential set-up.
Various Comparator specifications are listed below:
Propagation Delay -The time difference between the input crossing the reference voltage and the output changing the logic state. Generally, comparators are fast
Input Offset -The difference between the input voltages at the instance where output voltage equals zero volts
Gain–Ideal Comparator has infinite gain and output jumps from low to high at a specific difference in input voltage. Ideal comparators will have a linear transfer curve.
There are multiple other parameters like output swing, Output type, input and output current and impedance but we will focus on above including hysteresis.
This webinar will discuss all design, layout and specification details using ngspice, Xschem and Magic
Who this course is for:
- Beginner who is curious to know about circuit design and layout
- Physical Design Professionals curious to know about IP design
Tips on order in which you need to learn VLSI and become a CHAMPION:
If I would had been you, I would had started with Physical Design and Physical design webinar course where I understand the entire flow first, then would have moved to CTS-1 and CTS-2 to look into details of how the clock is been built.
Then, as you all know how crosstalk impacts functioning at lower nodes, I would gone for Signal Integrity course to understand impacts of scaling and fix them. Once I do that, I would want to know how to analyze performance of my design and I would have gone for STA-1, STA-2 and Timing ECO webinar courses, respectively
Once you STA, there’s an internal curiosity which rises, and wants us to understand, what goes inside timing analysis at transistor level. To full-fill that, I would had taken Circuit design and SPICE simulations Part 1 and Part 2 courses.
And finally, to understand pre-placed cells, IP’s and STA in even more detail, I would have taken custom layout course and Library Characterization course
All of above needs to be implemented using a CAD tool and needs to be done faster, for which I would have written TCL or perl scripts. So for that, I would start to learn TCL-Part1 and TCL-Part2 courses, at very beginning or in middle
Finally, if I want to learn RTL and synthesis, from specifications to layout, RISC-V ISA course will teach the best way to define specs for a complex system like microprocessor
Connect with me for more guidance !!
Hope you enjoy the session best of luck for future
Kunal Ghosh is the Director and co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd. Prior to launching VSD in 2017, Kunal held several technical leadership positions at Qualcomm's Test-chip business unit. He joined Qualcomm in 2010. He led the Physical design and STA flow development of 28nm, 16nm test-chips. At 2013, he joined Cadence as Lead Sales Application engineer for Tempus STA tool. Kunal holds a Masters degree in Electrical Engineering from Indian Institute of Technology (IIT), Bombay, India and specialized in VLSI Design & Nanotechnology.
Hands on with Technology @
1) MSM (mobile station mode chips) - MSM chips are used for CDMA modulation/demodulation. It consists of DSP’s and microprocessors for running applications such as web-browsing, video conferencing, multimedia services, etc.
2) Memory test chips - Memory test chips are used to validate functionality of 28nm custom/compiler memory as well as characterize their timing, power and yield.
3) DDR-PHY test chips - DDR-PHY test chips are basically tested for high speed data transfer
4) Timing and physical design Flow development for 130nm MOSFET technology node till 16nm FinFET technology node.
5) “IR aware STA” and “Low power STA”
6) Analyzed STA engine behavior for design size up to 850 million instance count ACADEMIC
1) Research Assistant to Prof. Richard Pinto and Prof. Anil Kottantharayil on “Sub-100nm optimization using Electron Beam Lithography”, which intended to optimize RAITH-150TWO Electron Beam Lithography tool and the process conditions to attain minimum resolution, use the mix-and-match capabilities of the tool for sub-100nm MOSFET fabrication and generate mask plates for feature sizes above 500nm.
2) Research Assistant to with Prof. Madhav Desai, to characterize RTL, generated from C-to-RTL AHIR compiler, in terms of power, performance and area. This was done by passing RTL, generated from AHIR compiler, through standard ASIC tool chain like synthesis and place & route. The resulting netlist out of PNR was characterized using standard software
1) “A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems” submitted in the conference “13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France”
2) Concurrent + Distributed MMMC STA for 'N' views
3) Signoff Timing and Leakage Optimization On 18M Instance Count Design With 8000 Clocks and Replicated Modules Using Master Clone Methodology With EDI Cockpit
4) Placement-aware ECO Methodology - No Slacking on Slack
Malay has worked as software engineer for more than 15 years. He completed his Masters in Physics from Michigan State University in 2013. He has worked on multiple projects involving Software, Firmware and embedded systems.
He has a good understanding of digital electronics, RTL Design, Synthesis and Static Timing Analysis. He is recently working on Analog physical design projects using Sky130.