VSD - Embedded-UVM

Discover embedded UVM, an open source verification language designed to tackle verification challenges as Moore's law slows, enabling multi-threaded simulations, free and open source silicon, and cloud-based continuous integration.

Explore variation trends in data network and compute performance, and how embedded UVM extends verification to open source hardware, bridging hardware and software to meet high bandwidth demands.

Explore testbenches for system-level verification and hardware accelerators, showing how FPGA-based and Verilog-based designs accelerate software algorithms through hardware and emulation, with a focus on verification and simulation.

Explore hardware accelerators from a verification perspective, focusing on mapping hybrid IP and verification IP to system level tests, UVM standardization, and integration challenges across vendors.

Demonstrate embedded UVM for hardware accelerators, enabling deployment-time tests on embedded processors and FPGA accelerators, with open source testing, SystemC considerations, and integration into software.

Join a live q&a session on how Embedded-UVM handles multi-threading and multiple simulations, including automatic garbage collection, C++ and D language compatibility, and the line-by-line design approach.

Explore how Embedded UVM runs in EMU environments across processors and small devices, enabling generation of hybrid patterns, DMA streaming, and FPGA-based emulation on Raspberry Pi and OS-based systems.

Explore embedded UVM architecture with a bottom-up ESPN-based simulation engine, API compatibility, and multiple UVM routes, enabling cross-platform verification from Windows to Android.

Explore embedded UVM innovations for multicore verification, enabling portable, parallel test benches that run on emulation and system simulation while sharing data with safe locking.

Explore how multicore e-UVM uses synchronization locks to safely manage data shared by multiple assignments, delivering performance gains through embedded, shared object programming.

Demonstrate productivity features of the D language, including dynamic and multi-dimensional arrays and constraints, to improve verification modeling and RTL simulation interfacing with embedded UVM.

Explore embedded uvm powered emulation using fpga-based platforms, level shifting, and gpo-driven test benches, with hands-on demonstrations of mapping designs onto fpga and observing waveforms.

Watch a testbench simulation demo using an Avalon streaming bus as the dut, illustrating how to push a data sequence into the design and validate the output with uvm.

Explore the OSI model of communication and how UVM transactions are represented as layered sequence items, linking mac and IP packets, payloads, and Avalon interfaces.

Examine testbench architecture for verilog co-simulation in embedded uvm, showing how drivers and monitors drive and capture signals through sequencers, from dcp packets to ip packets, mac layer, and ethernet.

Learn how to randomize a single object and reuse it across sequences in UVM, clone versus copy, and print transactions for debugging in Avalon streaming.

Explore how Embedded-UVM builds verification environments with agents, monitors, drivers, and scoreboards, and compare it to system verilog UVM, focusing on alignment, factory constructs, and parallel test benches.

Join a live Q&A on the E-UVM environment, exploring interfacing multiple boards and sensors, and comparing DPA and API approaches for verification and model compatibility.

Examine the avst_keccak protocol and the shift from abc to a standardized streaming interface with Avalon streaming, plus a reference model and C interop for FPGA emulation.

Explore functional details, control & status, data map, and input/output handling within an Avalon memory-mapped design, including framing, padding, and sequencing of data.

Understand and run the sha3 core testbench on an avalon-m bus, implementing read/write functions, integrating the monitor and scoreboard, and executing 100 transactions on an fpga kit in 12 seconds.

Demonstrates booting a DE10-Nano Cyclone V FPGA board, connecting camera and network, and mapping the Avalon bus to virtual memory for hardware–software integration.

Experience a live code debug and emulation session that compiles the embedded uvm library, runs an executable on hardware emulation, and shows speedups over software simulation with 10,000 transactions.

Explore the assignment problem by converting an Avalon-based test bench to excite transactions, outlining steps, a two-week timeline, and how to document and submit solutions.