VSD - Design process linkages and components in CMOS process

Name: VSD - Design process linkages and components in CMOS process
Rating: 4.2 (136 reviews)

Ever wondered what happens post SoC design? And how it happens?

Created byKunal Ghosh

Last updated 8/2024

English

English [Auto],

What you'll learn

Industrial Analog design
Industrial CMOS process
Issues and challenges in deep sub-micron technology
Design analog components in standard CMOS process

Course content

3 sections • 11 lectures • 1h 7m total length

Introduction3:30
Explore how the CMOS design process links logic, floor planning, and clock distribution. Identify the common library, standard cells, gates, and IP across steps.

Analog and digital design flow8:45
Explore the analog and digital design flow in CMOS, from top-down specifications and behavior models to block architecture, interfaces, schematic entry, simulation, layout, and physical verification.
Introduction to real 4-metal PDK9:30
Explore how real 4-metal PDKs link circuit design to fabrication, covering process choices, device models, metal layers, and operating ranges for reliable manufacture.
General cross-section in 180nm tech node and PDK's8:38
Examine a general cross-section of a 180 nm CMOS stack with metal layers and dielectrics, guided by PDKs. Understand how process variations and temperature affect design rules and parasitics.
PDK description, technology file and Pcells7:47
Explore the CMOS process design kit (pdk) description, technology files and pcells, including layer concepts, schematic versus layout, device models, and integration with simulations.

Model Files5:20
Explore bin-based compact MOS modeling across channel lengths and widths, covering saturation, linear, and inversion regions, driven by TowerJazz SPICE data and silicon-level PDK verification.
Legal Devices - MOSFETs Diodes Resistors6:04
Explore mosfets, diodes, and resistors in a triple-well cmos process, including n-well and p-well implants, sheet resistivity, and salicide contacts, with process design kit context.
Bipolar Devices And Capacitors2:35
Explore bipolar devices in CMOS processes, including non scalable BJT sizes and silicon germanium CMOS options, plus fringe and MIM capacitors to save silicon area.
NMOS Parameters And Standard Cell Library4:31
Examine NMOS transistor parameters and Ft variability using a common-source amplifier example, and understand standard cell libraries with testability features across voltage and temperature corners.
Memory IP And IO Library5:19
Analyze SRAM and memory compiler options, flash memory, and NVMe for compact, fast memory near the circuit, and review IO library pads, standard cells, flip-flop timing, and 1.8 μm CMOS targets.
Design Rule Checks5:19
Master CMOS design rules defined by the PDK, including minimum width, spacing, and extension constraints. Explore layout versus schematic checks, antenna rules, and parasitic models essential for reliability.

Requirements

Physical design and custom layout knowledge is nice to have
Should have knowledge on basic digital design and logic gates
Nice to have awareness about VLSI design basics and SoC design

Description

HS Jatana, with a distinguished career spanning over three decades in the VLSI industry, brings a wealth of experience and expertise to this course. Having worked at Rockwell Semiconductor in the USA, he has made significant contributions to process development and integration, device testing and characterization, and IC design. His hands-on experience in these critical areas has shaped his deep understanding of the intricacies of semiconductor technology. Currently, as the Group Head at the Semiconductor Laboratory (SCL), Jatana continues to lead and innovate in the field.

This course offers a comprehensive overview of basic analog and digital design flows from a manufacturing perspective, with a particular focus on the nuances that practitioners encounter in real-world applications. Key topics include Process Design Kits (PDKs), Pcells, and detailed insights into the 180nm technology node, including cross-sectional views and practical examples.

The course also delves into the various components available in a standard CMOS process. It explains the basic structures of different elements and how they are realized in the manufacturing process. Special emphasis is placed on passive components, which are crucial in any mixed-signal design. Participants will explore the features, advantages, and disadvantages of these passive elements, gaining a thorough understanding of their role in modern VLSI design.

Who this course is for:

VLSI design fresher who is curious for design manufacutring processes
Experienced SoC design professionals who is curious to know what happens inside CMOS manufacturing process

VSD - Design process linkages and components in CMOS process

What you'll learn

Explore related topics

Course content

Introduction1 lecture • 4min

Steps involved from design to manufacturing4 lectures • 35min

Devices and Model Files6 lectures • 29min

Requirements

Description

Who this course is for: