VSD - Design process linkages and components in CMOS process

HS Jatana, with a distinguished career spanning over three decades in the VLSI industry, brings a wealth of experience and expertise to this course. Having worked at Rockwell Semiconductor in the USA, he has made significant contributions to process development and integration, device testing and characterization, and IC design. His hands-on experience in these critical areas has shaped his deep understanding of the intricacies of semiconductor technology. Currently, as the Group Head at the Semiconductor Laboratory (SCL), Jatana continues to lead and innovate in the field.

This course offers a comprehensive overview of basic analog and digital design flows from a manufacturing perspective, with a particular focus on the nuances that practitioners encounter in real-world applications. Key topics include Process Design Kits (PDKs), Pcells, and detailed insights into the 180nm technology node, including cross-sectional views and practical examples.

The course also delves into the various components available in a standard CMOS process. It explains the basic structures of different elements and how they are realized in the manufacturing process. Special emphasis is placed on passive components, which are crucial in any mixed-signal design. Participants will explore the features, advantages, and disadvantages of these passive elements, gaining a thorough understanding of their role in modern VLSI design.