VLSI DFT Basics: From Industry Perspective

Name: VLSI DFT Basics: From Industry Perspective
Rating: 4.4 (95 reviews)

The purpose of DFT testing in VLSI along with industry standard DFT implementation flows

Created byAwais Hussain

Last updated 9/2025

English

What you'll learn

The purpose of DFT testing in VLSI and its role in reliable chip manufacturing
The chip design flow and how DFT integrates into chip design flow
Common manufacturing defects and fault models (stuck-at, transition, IDDQ, path delay)
Introduction to core DFT techniques including SCAN, MBIST, and Boundary Scan
How analog IPs are tested — a topic rarely covered in other courses
Never taught before industry-standard DFT implementation flow used in real chip projects

Course content

7 sections • 25 lectures • 3h 5m total length

Introduction15:38
This video provides introduction to what you will learn in this course and how this course is different from other DFT courses.

Chip Design Flow-RTL to GDSII15:41
Explore how designers move from design specifications to RTL coding, synthesis, and GDSII tapeout, including DFT integration, floor planning, LVS, and foundry handoff.
Purpose of Testing9:15
Types of Testing20:50
Explore various RTL to GDSII tests, from functional verification to structural DFT, memory BIST, and parametric and burn-in tests, linking faults to manufacturing and yield.

Manufacturing Defects4:38
Fault Modeling and Types4:41
Define fault modeling in DFT and differentiate fault, defect, error, and failure, and show how test vectors diagnose faults in IC designs.
Stuck-at Fault Model3:44
Discover the stuck-at fault model in VLSI DFT basics, and explore zero and one stuck faults, node-level faults, and DC patterns used to detect them.
Transition Fault Model2:47
IDDQ Fault Model2:08
Explain the iddq fault model, where a powered-on chip with minimal activity reaches a quiescent state and draws near-zero current, with deviations indicating faults.
Path Delay Fault Model2:54
Explore the path delay fault model and how faults along a data path affect timing on timing critical paths; contrast with transition faults that target individual nodes.
Cell-Aware Fault Model1:04
Explore the cell-aware, or self-aware, fault model that detects internal faults inside cells, essential for deep submicron nodes like 3 nm and 5 nm, unlike stuck-at or transition fault models.

Introduction to Basics of Testing Methods Section1:10
Introduction of Basics of Testing Methods1:10
Explore the basics of testing methods for modern chips, covering chip building blocks, logic testing via scan, memory built‑in self‑test, boundary scan diagnosis, and new analog ips testing.
Building Blocks of Chip8:28
Identify the four building blocks of a chip, including analog logic, digital logic, memories, and I/o pads, and explain mixed-signal blocks as blends of analog and digital.
Memory BIST (MBIST)11:11
Explore MBIST-based memory testing for SRAM, DRAM, ROM, and embedded flash. Identify stuck-at, transition, and data retention faults using five MBIST steps: generate data, address, read, and compare.
Boundary Scan Diagnosis (BSD)13:36
Explore boundary scan diagnosis to test chip boundaries using IEEE JTAG boundary scan, enabling testing of internal blocks with few I/O pins.
SCAN31:34
Learn how scan testing enables digital logic, memory, boundary scan, and analog IPS testing in chips, using scan flip-flops, scan chains, and scan codecs for efficient pattern generation and validation.
Analog IPs Testing6:46

Basic DFT Implementation Flows used in Industry5:54
Explore industry oriented dft implementation flows, covering scan insertion, memory based insertion, and boundary scan, within the rtl to gdsii cycle and emphasis on timing analysis and design finalization.
Basic SCAN Insertion Flow8:33
MBIST Insertion Flow2:43
Explore mbist insertion flow for memory based testing, with planning, iterative lec checks, and refreshed timing constraints to validate memory based design meets test timing.
BSD Insertion Flow1:11
Analog IP Test Mode Insertion Flow5:44
Learn two industry methods for analog ip test mode insertion in vlsi dft: using muxes during rtl-to-dft and boundary-scan insertion, with stage-wise verification across sta, scan, and boundary-scan.
Different Tools Usage in DFT2:46
Discover the range of dft tools for scan insertion, memory-based and boundary-scan insertion, atpg, test-pattern generation, static timing analysis, and synthesis workflows.

Requirements

Basic digital logic design knowledge (logic gates, flip-flops, combinational vs. sequential circuits)
Familiarity with HDL (Verilog or VHDL) at an introductory level
Basic awareness of the VLSI design flow (RTL to GDSII)
General understanding of semiconductor basics (what is a chip, role of transistors, CMOS)
Comfortable with timing concepts such as setup/hold, clock, and reset

Description

VLSI DFT Basics: From Industry Perspective

Unlock the world of Design-for-Test (DFT) with this industry-oriented course designed for engineers, graduate students, and VLSI enthusiasts. DFT is a critical part of modern chip design, ensuring that your silicon is manufacturable, reliable, and testable.

In this course, you’ll learn the concepts and methods used by top semiconductor companies, presented in simple, easy-to-understand language. Unlike traditional courses, this course also covers analog IP testing and DFT implementation flows—a topic often missing in standard DFT training.

You’ll gain hands-on understanding of:

Why testing is crucial and the goals it serves
The types of manufacturing defects and fault models
Core DFT methods including SCAN, MBIST, and boundary scan
How DFT is integrated into the industry-standard chip design flow

Whether you’re a fresh graduate, RTL/backend engineer, verification engineer, or aspiring DFT professional, this condensed curriculum delivers months of industry knowledge in just a few hours.

By the end of this course, you’ll be ready to understand basics of DFT and DFT implementation flows used in industry in real-world chip designs.

This course was designed personally by me as it took me months to understand about VLSI DFT and went through so many books, trainings, user guides, and a lot more. I have condenesed all of my months of learning into this short course, which I also present in chip companies.

Who this course is for:

Undergraduates, fresh graduates or early-career engineers looking to build a foundation in DFT
RTL, synthesis, and physical design (place & route) engineers seeking DFT awareness
DFT engineers and flow developers aiming to strengthen foundational knowledge
Graduate students aspiring to build a career in the DFT domain

VLSI DFT Basics: From Industry Perspective

What you'll learn

Explore related topics

Course content

Introduction1 lecture • 16min

The Purpose of Testing (Why?)3 lectures • 46min

The Target of Testing (What?)7 lectures • 22min

The Basics of Testing Methods (How?)7 lectures • 1hr 14min

Basic DFT Implementation Flows used in Industry6 lectures • 27min

Conclusion1 lecture • 1min

Test your knowledge0

Requirements

Description

Who this course is for: