VSD - Static Timing Analysis - I

convert logic gates into nodes by building a timing graph and analyzing setup and clock delays to understand single-clock timing in static timing analysis.

This lecture explains constructing a timing graph for static timing analysis, defines actual arrival time (AAT), and demonstrates how to compute delays from launch to capture flops for setup analysis.

Compute the required arrival time (RAT) for each node and analyze slack, including negative slack, to identify timing bottlenecks and guide engineering changes.

Compute slack by comparing required travel time with actual arrival time and introduce graph-based and pin-based analysis (GBA-PBA) to assess delays and guide optimizations.

Convert pins to nodes and compute AAT, RAT, and slack in a timing graph using pinboard conventions and unit delays.

Move to transistor-level circuitry for the launch flop and capture flop, analyzing clock-to-Q delays, clock buffering, and setup timing, with a look into transistor-level mux implementation.

Explore how negative and positive latches form a flip-flop, and calculate library setup time and clock-to-delay using inverter and transmission-gate delays.

Analyze jitter extraction and its effect on setup timing analysis, including noise margin, signal integrity, and clock period variation. Model uncertainty, account for data arrival time, and evaluate slack.

Convert graphical timing representations into textual formats for setup analysis and learn to read industry-standard timing reports. Explore how delays, nets, and clock data inform setup timings.

Apply hold analysis with real clocks to assess launch and capture flop timing, hold time, and data validity after clock edges, highlighting uncertainty and differences from setup analysis.

Convert the graphical hold analysis into a textual representation, using the same data flow from launch flop to the net and presenting the minimum delays and uncertainties involved.

Explore how the etching process, a key fabrication step, introduces variation in transistor structures—diffusion regions, polysilicon, and gate overlap—affecting inverter behavior and timing.

Explore oxide thickness variation as a source of variation in MOSFET gate oxide, its impact on oxide capacitance and drain current, and implications for inverter timing in static timing analysis.

Explore how resistance, drain current and capacitor charging shape output delay in MOSFET circuits, revealing nonlinear resistance, inverter delay variation, and on-chip process variations relevant to static timing analysis.

Explore OCV based setup timing analysis and Demming analysis concepts, examining 20 percent variations in data and delays and the effects of clock push or pull on slack and frequency.

Explore setup timing analysis after pessimism removal, focusing on common clock blocks, OCV delays, and achieving positive slack at the target frequency.

Explore OCV based hold timing analysis to quantify worst‑case data and clock delays under 20 percent variations, assessing clock edge shifts and hold violations across the retimed chip.

Understand that core timing analysis concepts stay constant across checks, while the specific checks vary, and anticipate the next course continuing with static timing analysis.